bcmsysport.c 74 KB

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  1. /*
  2. * Broadcom BCM7xxx System Port Ethernet MAC driver
  3. *
  4. * Copyright (C) 2014 Broadcom Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/etherdevice.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/of.h>
  19. #include <linux/of_net.h>
  20. #include <linux/of_mdio.h>
  21. #include <linux/phy.h>
  22. #include <linux/phy_fixed.h>
  23. #include <net/dsa.h>
  24. #include <net/ip.h>
  25. #include <net/ipv6.h>
  26. #include "bcmsysport.h"
  27. /* I/O accessors register helpers */
  28. #define BCM_SYSPORT_IO_MACRO(name, offset) \
  29. static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
  30. { \
  31. u32 reg = readl_relaxed(priv->base + offset + off); \
  32. return reg; \
  33. } \
  34. static inline void name##_writel(struct bcm_sysport_priv *priv, \
  35. u32 val, u32 off) \
  36. { \
  37. writel_relaxed(val, priv->base + offset + off); \
  38. } \
  39. BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
  40. BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
  41. BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
  42. BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET);
  43. BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
  44. BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
  45. BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
  46. BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
  47. BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
  48. BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
  49. /* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact
  50. * same layout, except it has been moved by 4 bytes up, *sigh*
  51. */
  52. static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off)
  53. {
  54. if (priv->is_lite && off >= RDMA_STATUS)
  55. off += 4;
  56. return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off);
  57. }
  58. static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off)
  59. {
  60. if (priv->is_lite && off >= RDMA_STATUS)
  61. off += 4;
  62. writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);
  63. }
  64. static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit)
  65. {
  66. if (!priv->is_lite) {
  67. return BIT(bit);
  68. } else {
  69. if (bit >= ACB_ALGO)
  70. return BIT(bit + 1);
  71. else
  72. return BIT(bit);
  73. }
  74. }
  75. /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
  76. * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
  77. */
  78. #define BCM_SYSPORT_INTR_L2(which) \
  79. static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
  80. u32 mask) \
  81. { \
  82. priv->irq##which##_mask &= ~(mask); \
  83. intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
  84. } \
  85. static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
  86. u32 mask) \
  87. { \
  88. intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
  89. priv->irq##which##_mask |= (mask); \
  90. } \
  91. BCM_SYSPORT_INTR_L2(0)
  92. BCM_SYSPORT_INTR_L2(1)
  93. /* Register accesses to GISB/RBUS registers are expensive (few hundred
  94. * nanoseconds), so keep the check for 64-bits explicit here to save
  95. * one register write per-packet on 32-bits platforms.
  96. */
  97. static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
  98. void __iomem *d,
  99. dma_addr_t addr)
  100. {
  101. #ifdef CONFIG_PHYS_ADDR_T_64BIT
  102. writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
  103. d + DESC_ADDR_HI_STATUS_LEN);
  104. #endif
  105. writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);
  106. }
  107. static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
  108. struct dma_desc *desc,
  109. unsigned int port)
  110. {
  111. /* Ports are latched, so write upper address first */
  112. tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
  113. tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
  114. }
  115. /* Ethtool operations */
  116. static int bcm_sysport_set_rx_csum(struct net_device *dev,
  117. netdev_features_t wanted)
  118. {
  119. struct bcm_sysport_priv *priv = netdev_priv(dev);
  120. u32 reg;
  121. priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
  122. reg = rxchk_readl(priv, RXCHK_CONTROL);
  123. /* Clear L2 header checks, which would prevent BPDUs
  124. * from being received.
  125. */
  126. reg &= ~RXCHK_L2_HDR_DIS;
  127. if (priv->rx_chk_en)
  128. reg |= RXCHK_EN;
  129. else
  130. reg &= ~RXCHK_EN;
  131. /* If UniMAC forwards CRC, we need to skip over it to get
  132. * a valid CHK bit to be set in the per-packet status word
  133. */
  134. if (priv->rx_chk_en && priv->crc_fwd)
  135. reg |= RXCHK_SKIP_FCS;
  136. else
  137. reg &= ~RXCHK_SKIP_FCS;
  138. /* If Broadcom tags are enabled (e.g: using a switch), make
  139. * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
  140. * tag after the Ethernet MAC Source Address.
  141. */
  142. if (netdev_uses_dsa(dev))
  143. reg |= RXCHK_BRCM_TAG_EN;
  144. else
  145. reg &= ~RXCHK_BRCM_TAG_EN;
  146. rxchk_writel(priv, reg, RXCHK_CONTROL);
  147. return 0;
  148. }
  149. static int bcm_sysport_set_tx_csum(struct net_device *dev,
  150. netdev_features_t wanted)
  151. {
  152. struct bcm_sysport_priv *priv = netdev_priv(dev);
  153. u32 reg;
  154. /* Hardware transmit checksum requires us to enable the Transmit status
  155. * block prepended to the packet contents
  156. */
  157. priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
  158. reg = tdma_readl(priv, TDMA_CONTROL);
  159. if (priv->tsb_en)
  160. reg |= tdma_control_bit(priv, TSB_EN);
  161. else
  162. reg &= ~tdma_control_bit(priv, TSB_EN);
  163. tdma_writel(priv, reg, TDMA_CONTROL);
  164. return 0;
  165. }
  166. static int bcm_sysport_set_features(struct net_device *dev,
  167. netdev_features_t features)
  168. {
  169. netdev_features_t changed = features ^ dev->features;
  170. netdev_features_t wanted = dev->wanted_features;
  171. int ret = 0;
  172. if (changed & NETIF_F_RXCSUM)
  173. ret = bcm_sysport_set_rx_csum(dev, wanted);
  174. if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
  175. ret = bcm_sysport_set_tx_csum(dev, wanted);
  176. return ret;
  177. }
  178. /* Hardware counters must be kept in sync because the order/offset
  179. * is important here (order in structure declaration = order in hardware)
  180. */
  181. static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
  182. /* general stats */
  183. STAT_NETDEV64(rx_packets),
  184. STAT_NETDEV64(tx_packets),
  185. STAT_NETDEV64(rx_bytes),
  186. STAT_NETDEV64(tx_bytes),
  187. STAT_NETDEV(rx_errors),
  188. STAT_NETDEV(tx_errors),
  189. STAT_NETDEV(rx_dropped),
  190. STAT_NETDEV(tx_dropped),
  191. STAT_NETDEV(multicast),
  192. /* UniMAC RSV counters */
  193. STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
  194. STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
  195. STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
  196. STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
  197. STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
  198. STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
  199. STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
  200. STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
  201. STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
  202. STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
  203. STAT_MIB_RX("rx_pkts", mib.rx.pkt),
  204. STAT_MIB_RX("rx_bytes", mib.rx.bytes),
  205. STAT_MIB_RX("rx_multicast", mib.rx.mca),
  206. STAT_MIB_RX("rx_broadcast", mib.rx.bca),
  207. STAT_MIB_RX("rx_fcs", mib.rx.fcs),
  208. STAT_MIB_RX("rx_control", mib.rx.cf),
  209. STAT_MIB_RX("rx_pause", mib.rx.pf),
  210. STAT_MIB_RX("rx_unknown", mib.rx.uo),
  211. STAT_MIB_RX("rx_align", mib.rx.aln),
  212. STAT_MIB_RX("rx_outrange", mib.rx.flr),
  213. STAT_MIB_RX("rx_code", mib.rx.cde),
  214. STAT_MIB_RX("rx_carrier", mib.rx.fcr),
  215. STAT_MIB_RX("rx_oversize", mib.rx.ovr),
  216. STAT_MIB_RX("rx_jabber", mib.rx.jbr),
  217. STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
  218. STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
  219. STAT_MIB_RX("rx_unicast", mib.rx.uc),
  220. STAT_MIB_RX("rx_ppp", mib.rx.ppp),
  221. STAT_MIB_RX("rx_crc", mib.rx.rcrc),
  222. /* UniMAC TSV counters */
  223. STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
  224. STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
  225. STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
  226. STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
  227. STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
  228. STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
  229. STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
  230. STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
  231. STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
  232. STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
  233. STAT_MIB_TX("tx_pkts", mib.tx.pkts),
  234. STAT_MIB_TX("tx_multicast", mib.tx.mca),
  235. STAT_MIB_TX("tx_broadcast", mib.tx.bca),
  236. STAT_MIB_TX("tx_pause", mib.tx.pf),
  237. STAT_MIB_TX("tx_control", mib.tx.cf),
  238. STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
  239. STAT_MIB_TX("tx_oversize", mib.tx.ovr),
  240. STAT_MIB_TX("tx_defer", mib.tx.drf),
  241. STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
  242. STAT_MIB_TX("tx_single_col", mib.tx.scl),
  243. STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
  244. STAT_MIB_TX("tx_late_col", mib.tx.lcl),
  245. STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
  246. STAT_MIB_TX("tx_frags", mib.tx.frg),
  247. STAT_MIB_TX("tx_total_col", mib.tx.ncl),
  248. STAT_MIB_TX("tx_jabber", mib.tx.jbr),
  249. STAT_MIB_TX("tx_bytes", mib.tx.bytes),
  250. STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
  251. STAT_MIB_TX("tx_unicast", mib.tx.uc),
  252. /* UniMAC RUNT counters */
  253. STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
  254. STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
  255. STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
  256. STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
  257. /* RXCHK misc statistics */
  258. STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
  259. STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
  260. RXCHK_OTHER_DISC_CNTR),
  261. /* RBUF misc statistics */
  262. STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
  263. STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
  264. STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
  265. STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
  266. STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
  267. /* Per TX-queue statistics are dynamically appended */
  268. };
  269. #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
  270. static void bcm_sysport_get_drvinfo(struct net_device *dev,
  271. struct ethtool_drvinfo *info)
  272. {
  273. strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
  274. strlcpy(info->version, "0.1", sizeof(info->version));
  275. strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
  276. }
  277. static u32 bcm_sysport_get_msglvl(struct net_device *dev)
  278. {
  279. struct bcm_sysport_priv *priv = netdev_priv(dev);
  280. return priv->msg_enable;
  281. }
  282. static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
  283. {
  284. struct bcm_sysport_priv *priv = netdev_priv(dev);
  285. priv->msg_enable = enable;
  286. }
  287. static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type)
  288. {
  289. switch (type) {
  290. case BCM_SYSPORT_STAT_NETDEV:
  291. case BCM_SYSPORT_STAT_NETDEV64:
  292. case BCM_SYSPORT_STAT_RXCHK:
  293. case BCM_SYSPORT_STAT_RBUF:
  294. case BCM_SYSPORT_STAT_SOFT:
  295. return true;
  296. default:
  297. return false;
  298. }
  299. }
  300. static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
  301. {
  302. struct bcm_sysport_priv *priv = netdev_priv(dev);
  303. const struct bcm_sysport_stats *s;
  304. unsigned int i, j;
  305. switch (string_set) {
  306. case ETH_SS_STATS:
  307. for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
  308. s = &bcm_sysport_gstrings_stats[i];
  309. if (priv->is_lite &&
  310. !bcm_sysport_lite_stat_valid(s->type))
  311. continue;
  312. j++;
  313. }
  314. /* Include per-queue statistics */
  315. return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
  316. default:
  317. return -EOPNOTSUPP;
  318. }
  319. }
  320. static void bcm_sysport_get_strings(struct net_device *dev,
  321. u32 stringset, u8 *data)
  322. {
  323. struct bcm_sysport_priv *priv = netdev_priv(dev);
  324. const struct bcm_sysport_stats *s;
  325. char buf[128];
  326. int i, j;
  327. switch (stringset) {
  328. case ETH_SS_STATS:
  329. for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
  330. s = &bcm_sysport_gstrings_stats[i];
  331. if (priv->is_lite &&
  332. !bcm_sysport_lite_stat_valid(s->type))
  333. continue;
  334. memcpy(data + j * ETH_GSTRING_LEN, s->stat_string,
  335. ETH_GSTRING_LEN);
  336. j++;
  337. }
  338. for (i = 0; i < dev->num_tx_queues; i++) {
  339. snprintf(buf, sizeof(buf), "txq%d_packets", i);
  340. memcpy(data + j * ETH_GSTRING_LEN, buf,
  341. ETH_GSTRING_LEN);
  342. j++;
  343. snprintf(buf, sizeof(buf), "txq%d_bytes", i);
  344. memcpy(data + j * ETH_GSTRING_LEN, buf,
  345. ETH_GSTRING_LEN);
  346. j++;
  347. }
  348. break;
  349. default:
  350. break;
  351. }
  352. }
  353. static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
  354. {
  355. int i, j = 0;
  356. for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
  357. const struct bcm_sysport_stats *s;
  358. u8 offset = 0;
  359. u32 val = 0;
  360. char *p;
  361. s = &bcm_sysport_gstrings_stats[i];
  362. switch (s->type) {
  363. case BCM_SYSPORT_STAT_NETDEV:
  364. case BCM_SYSPORT_STAT_NETDEV64:
  365. case BCM_SYSPORT_STAT_SOFT:
  366. continue;
  367. case BCM_SYSPORT_STAT_MIB_RX:
  368. case BCM_SYSPORT_STAT_MIB_TX:
  369. case BCM_SYSPORT_STAT_RUNT:
  370. if (priv->is_lite)
  371. continue;
  372. if (s->type != BCM_SYSPORT_STAT_MIB_RX)
  373. offset = UMAC_MIB_STAT_OFFSET;
  374. val = umac_readl(priv, UMAC_MIB_START + j + offset);
  375. break;
  376. case BCM_SYSPORT_STAT_RXCHK:
  377. val = rxchk_readl(priv, s->reg_offset);
  378. if (val == ~0)
  379. rxchk_writel(priv, 0, s->reg_offset);
  380. break;
  381. case BCM_SYSPORT_STAT_RBUF:
  382. val = rbuf_readl(priv, s->reg_offset);
  383. if (val == ~0)
  384. rbuf_writel(priv, 0, s->reg_offset);
  385. break;
  386. }
  387. j += s->stat_sizeof;
  388. p = (char *)priv + s->stat_offset;
  389. *(u32 *)p = val;
  390. }
  391. netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
  392. }
  393. static void bcm_sysport_update_tx_stats(struct bcm_sysport_priv *priv,
  394. u64 *tx_bytes, u64 *tx_packets)
  395. {
  396. struct bcm_sysport_tx_ring *ring;
  397. u64 bytes = 0, packets = 0;
  398. unsigned int start;
  399. unsigned int q;
  400. for (q = 0; q < priv->netdev->num_tx_queues; q++) {
  401. ring = &priv->tx_rings[q];
  402. do {
  403. start = u64_stats_fetch_begin_irq(&priv->syncp);
  404. bytes = ring->bytes;
  405. packets = ring->packets;
  406. } while (u64_stats_fetch_retry_irq(&priv->syncp, start));
  407. *tx_bytes += bytes;
  408. *tx_packets += packets;
  409. }
  410. }
  411. static void bcm_sysport_get_stats(struct net_device *dev,
  412. struct ethtool_stats *stats, u64 *data)
  413. {
  414. struct bcm_sysport_priv *priv = netdev_priv(dev);
  415. struct bcm_sysport_stats64 *stats64 = &priv->stats64;
  416. struct u64_stats_sync *syncp = &priv->syncp;
  417. struct bcm_sysport_tx_ring *ring;
  418. u64 tx_bytes = 0, tx_packets = 0;
  419. unsigned int start;
  420. int i, j;
  421. if (netif_running(dev)) {
  422. bcm_sysport_update_mib_counters(priv);
  423. bcm_sysport_update_tx_stats(priv, &tx_bytes, &tx_packets);
  424. stats64->tx_bytes = tx_bytes;
  425. stats64->tx_packets = tx_packets;
  426. }
  427. for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
  428. const struct bcm_sysport_stats *s;
  429. char *p;
  430. s = &bcm_sysport_gstrings_stats[i];
  431. if (s->type == BCM_SYSPORT_STAT_NETDEV)
  432. p = (char *)&dev->stats;
  433. else if (s->type == BCM_SYSPORT_STAT_NETDEV64)
  434. p = (char *)stats64;
  435. else
  436. p = (char *)priv;
  437. if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type))
  438. continue;
  439. p += s->stat_offset;
  440. if (s->stat_sizeof == sizeof(u64) &&
  441. s->type == BCM_SYSPORT_STAT_NETDEV64) {
  442. do {
  443. start = u64_stats_fetch_begin_irq(syncp);
  444. data[i] = *(u64 *)p;
  445. } while (u64_stats_fetch_retry_irq(syncp, start));
  446. } else
  447. data[i] = *(u32 *)p;
  448. j++;
  449. }
  450. /* For SYSTEMPORT Lite since we have holes in our statistics, j would
  451. * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it
  452. * needs to point to how many total statistics we have minus the
  453. * number of per TX queue statistics
  454. */
  455. j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) -
  456. dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
  457. for (i = 0; i < dev->num_tx_queues; i++) {
  458. ring = &priv->tx_rings[i];
  459. data[j] = ring->packets;
  460. j++;
  461. data[j] = ring->bytes;
  462. j++;
  463. }
  464. }
  465. static void bcm_sysport_get_wol(struct net_device *dev,
  466. struct ethtool_wolinfo *wol)
  467. {
  468. struct bcm_sysport_priv *priv = netdev_priv(dev);
  469. wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
  470. wol->wolopts = priv->wolopts;
  471. if (!(priv->wolopts & WAKE_MAGICSECURE))
  472. return;
  473. memcpy(wol->sopass, priv->sopass, sizeof(priv->sopass));
  474. }
  475. static int bcm_sysport_set_wol(struct net_device *dev,
  476. struct ethtool_wolinfo *wol)
  477. {
  478. struct bcm_sysport_priv *priv = netdev_priv(dev);
  479. struct device *kdev = &priv->pdev->dev;
  480. u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
  481. if (!device_can_wakeup(kdev))
  482. return -ENOTSUPP;
  483. if (wol->wolopts & ~supported)
  484. return -EINVAL;
  485. if (wol->wolopts & WAKE_MAGICSECURE)
  486. memcpy(priv->sopass, wol->sopass, sizeof(priv->sopass));
  487. /* Flag the device and relevant IRQ as wakeup capable */
  488. if (wol->wolopts) {
  489. device_set_wakeup_enable(kdev, 1);
  490. if (priv->wol_irq_disabled)
  491. enable_irq_wake(priv->wol_irq);
  492. priv->wol_irq_disabled = 0;
  493. } else {
  494. device_set_wakeup_enable(kdev, 0);
  495. /* Avoid unbalanced disable_irq_wake calls */
  496. if (!priv->wol_irq_disabled)
  497. disable_irq_wake(priv->wol_irq);
  498. priv->wol_irq_disabled = 1;
  499. }
  500. priv->wolopts = wol->wolopts;
  501. return 0;
  502. }
  503. static void bcm_sysport_set_rx_coalesce(struct bcm_sysport_priv *priv,
  504. u32 usecs, u32 pkts)
  505. {
  506. u32 reg;
  507. reg = rdma_readl(priv, RDMA_MBDONE_INTR);
  508. reg &= ~(RDMA_INTR_THRESH_MASK |
  509. RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
  510. reg |= pkts;
  511. reg |= DIV_ROUND_UP(usecs * 1000, 8192) << RDMA_TIMEOUT_SHIFT;
  512. rdma_writel(priv, reg, RDMA_MBDONE_INTR);
  513. }
  514. static void bcm_sysport_set_tx_coalesce(struct bcm_sysport_tx_ring *ring,
  515. struct ethtool_coalesce *ec)
  516. {
  517. struct bcm_sysport_priv *priv = ring->priv;
  518. u32 reg;
  519. reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(ring->index));
  520. reg &= ~(RING_INTR_THRESH_MASK |
  521. RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
  522. reg |= ec->tx_max_coalesced_frames;
  523. reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
  524. RING_TIMEOUT_SHIFT;
  525. tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(ring->index));
  526. }
  527. static int bcm_sysport_get_coalesce(struct net_device *dev,
  528. struct ethtool_coalesce *ec)
  529. {
  530. struct bcm_sysport_priv *priv = netdev_priv(dev);
  531. u32 reg;
  532. reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
  533. ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
  534. ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
  535. reg = rdma_readl(priv, RDMA_MBDONE_INTR);
  536. ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
  537. ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
  538. ec->use_adaptive_rx_coalesce = priv->dim.use_dim;
  539. return 0;
  540. }
  541. static int bcm_sysport_set_coalesce(struct net_device *dev,
  542. struct ethtool_coalesce *ec)
  543. {
  544. struct bcm_sysport_priv *priv = netdev_priv(dev);
  545. struct net_dim_cq_moder moder;
  546. u32 usecs, pkts;
  547. unsigned int i;
  548. /* Base system clock is 125Mhz, DMA timeout is this reference clock
  549. * divided by 1024, which yield roughly 8.192 us, our maximum value has
  550. * to fit in the RING_TIMEOUT_MASK (16 bits).
  551. */
  552. if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
  553. ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
  554. ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
  555. ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
  556. return -EINVAL;
  557. if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
  558. (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) ||
  559. ec->use_adaptive_tx_coalesce)
  560. return -EINVAL;
  561. for (i = 0; i < dev->num_tx_queues; i++)
  562. bcm_sysport_set_tx_coalesce(&priv->tx_rings[i], ec);
  563. priv->rx_coalesce_usecs = ec->rx_coalesce_usecs;
  564. priv->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  565. usecs = priv->rx_coalesce_usecs;
  566. pkts = priv->rx_max_coalesced_frames;
  567. if (ec->use_adaptive_rx_coalesce && !priv->dim.use_dim) {
  568. moder = net_dim_get_def_rx_moderation(priv->dim.dim.mode);
  569. usecs = moder.usec;
  570. pkts = moder.pkts;
  571. }
  572. priv->dim.use_dim = ec->use_adaptive_rx_coalesce;
  573. /* Apply desired coalescing parameters */
  574. bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
  575. return 0;
  576. }
  577. static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
  578. {
  579. dev_consume_skb_any(cb->skb);
  580. cb->skb = NULL;
  581. dma_unmap_addr_set(cb, dma_addr, 0);
  582. }
  583. static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
  584. struct bcm_sysport_cb *cb)
  585. {
  586. struct device *kdev = &priv->pdev->dev;
  587. struct net_device *ndev = priv->netdev;
  588. struct sk_buff *skb, *rx_skb;
  589. dma_addr_t mapping;
  590. /* Allocate a new SKB for a new packet */
  591. skb = __netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH,
  592. GFP_ATOMIC | __GFP_NOWARN);
  593. if (!skb) {
  594. priv->mib.alloc_rx_buff_failed++;
  595. netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
  596. return NULL;
  597. }
  598. mapping = dma_map_single(kdev, skb->data,
  599. RX_BUF_LENGTH, DMA_FROM_DEVICE);
  600. if (dma_mapping_error(kdev, mapping)) {
  601. priv->mib.rx_dma_failed++;
  602. dev_kfree_skb_any(skb);
  603. netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
  604. return NULL;
  605. }
  606. /* Grab the current SKB on the ring */
  607. rx_skb = cb->skb;
  608. if (likely(rx_skb))
  609. dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
  610. RX_BUF_LENGTH, DMA_FROM_DEVICE);
  611. /* Put the new SKB on the ring */
  612. cb->skb = skb;
  613. dma_unmap_addr_set(cb, dma_addr, mapping);
  614. dma_desc_set_addr(priv, cb->bd_addr, mapping);
  615. netif_dbg(priv, rx_status, ndev, "RX refill\n");
  616. /* Return the current SKB to the caller */
  617. return rx_skb;
  618. }
  619. static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
  620. {
  621. struct bcm_sysport_cb *cb;
  622. struct sk_buff *skb;
  623. unsigned int i;
  624. for (i = 0; i < priv->num_rx_bds; i++) {
  625. cb = &priv->rx_cbs[i];
  626. skb = bcm_sysport_rx_refill(priv, cb);
  627. if (skb)
  628. dev_kfree_skb(skb);
  629. if (!cb->skb)
  630. return -ENOMEM;
  631. }
  632. return 0;
  633. }
  634. /* Poll the hardware for up to budget packets to process */
  635. static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
  636. unsigned int budget)
  637. {
  638. struct bcm_sysport_stats64 *stats64 = &priv->stats64;
  639. struct net_device *ndev = priv->netdev;
  640. unsigned int processed = 0, to_process;
  641. unsigned int processed_bytes = 0;
  642. struct bcm_sysport_cb *cb;
  643. struct sk_buff *skb;
  644. unsigned int p_index;
  645. u16 len, status;
  646. struct bcm_rsb *rsb;
  647. /* Clear status before servicing to reduce spurious interrupts */
  648. intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR);
  649. /* Determine how much we should process since last call, SYSTEMPORT Lite
  650. * groups the producer and consumer indexes into the same 32-bit
  651. * which we access using RDMA_CONS_INDEX
  652. */
  653. if (!priv->is_lite)
  654. p_index = rdma_readl(priv, RDMA_PROD_INDEX);
  655. else
  656. p_index = rdma_readl(priv, RDMA_CONS_INDEX);
  657. p_index &= RDMA_PROD_INDEX_MASK;
  658. to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK;
  659. netif_dbg(priv, rx_status, ndev,
  660. "p_index=%d rx_c_index=%d to_process=%d\n",
  661. p_index, priv->rx_c_index, to_process);
  662. while ((processed < to_process) && (processed < budget)) {
  663. cb = &priv->rx_cbs[priv->rx_read_ptr];
  664. skb = bcm_sysport_rx_refill(priv, cb);
  665. /* We do not have a backing SKB, so we do not a corresponding
  666. * DMA mapping for this incoming packet since
  667. * bcm_sysport_rx_refill always either has both skb and mapping
  668. * or none.
  669. */
  670. if (unlikely(!skb)) {
  671. netif_err(priv, rx_err, ndev, "out of memory!\n");
  672. ndev->stats.rx_dropped++;
  673. ndev->stats.rx_errors++;
  674. goto next;
  675. }
  676. /* Extract the Receive Status Block prepended */
  677. rsb = (struct bcm_rsb *)skb->data;
  678. len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
  679. status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
  680. DESC_STATUS_MASK;
  681. netif_dbg(priv, rx_status, ndev,
  682. "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
  683. p_index, priv->rx_c_index, priv->rx_read_ptr,
  684. len, status);
  685. if (unlikely(len > RX_BUF_LENGTH)) {
  686. netif_err(priv, rx_status, ndev, "oversized packet\n");
  687. ndev->stats.rx_length_errors++;
  688. ndev->stats.rx_errors++;
  689. dev_kfree_skb_any(skb);
  690. goto next;
  691. }
  692. if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
  693. netif_err(priv, rx_status, ndev, "fragmented packet!\n");
  694. ndev->stats.rx_dropped++;
  695. ndev->stats.rx_errors++;
  696. dev_kfree_skb_any(skb);
  697. goto next;
  698. }
  699. if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
  700. netif_err(priv, rx_err, ndev, "error packet\n");
  701. if (status & RX_STATUS_OVFLOW)
  702. ndev->stats.rx_over_errors++;
  703. ndev->stats.rx_dropped++;
  704. ndev->stats.rx_errors++;
  705. dev_kfree_skb_any(skb);
  706. goto next;
  707. }
  708. skb_put(skb, len);
  709. /* Hardware validated our checksum */
  710. if (likely(status & DESC_L4_CSUM))
  711. skb->ip_summed = CHECKSUM_UNNECESSARY;
  712. /* Hardware pre-pends packets with 2bytes before Ethernet
  713. * header plus we have the Receive Status Block, strip off all
  714. * of this from the SKB.
  715. */
  716. skb_pull(skb, sizeof(*rsb) + 2);
  717. len -= (sizeof(*rsb) + 2);
  718. processed_bytes += len;
  719. /* UniMAC may forward CRC */
  720. if (priv->crc_fwd) {
  721. skb_trim(skb, len - ETH_FCS_LEN);
  722. len -= ETH_FCS_LEN;
  723. }
  724. skb->protocol = eth_type_trans(skb, ndev);
  725. ndev->stats.rx_packets++;
  726. ndev->stats.rx_bytes += len;
  727. u64_stats_update_begin(&priv->syncp);
  728. stats64->rx_packets++;
  729. stats64->rx_bytes += len;
  730. u64_stats_update_end(&priv->syncp);
  731. napi_gro_receive(&priv->napi, skb);
  732. next:
  733. processed++;
  734. priv->rx_read_ptr++;
  735. if (priv->rx_read_ptr == priv->num_rx_bds)
  736. priv->rx_read_ptr = 0;
  737. }
  738. priv->dim.packets = processed;
  739. priv->dim.bytes = processed_bytes;
  740. return processed;
  741. }
  742. static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring,
  743. struct bcm_sysport_cb *cb,
  744. unsigned int *bytes_compl,
  745. unsigned int *pkts_compl)
  746. {
  747. struct bcm_sysport_priv *priv = ring->priv;
  748. struct device *kdev = &priv->pdev->dev;
  749. if (cb->skb) {
  750. *bytes_compl += cb->skb->len;
  751. dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
  752. dma_unmap_len(cb, dma_len),
  753. DMA_TO_DEVICE);
  754. (*pkts_compl)++;
  755. bcm_sysport_free_cb(cb);
  756. /* SKB fragment */
  757. } else if (dma_unmap_addr(cb, dma_addr)) {
  758. *bytes_compl += dma_unmap_len(cb, dma_len);
  759. dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
  760. dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
  761. dma_unmap_addr_set(cb, dma_addr, 0);
  762. }
  763. }
  764. /* Reclaim queued SKBs for transmission completion, lockless version */
  765. static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
  766. struct bcm_sysport_tx_ring *ring)
  767. {
  768. unsigned int pkts_compl = 0, bytes_compl = 0;
  769. struct net_device *ndev = priv->netdev;
  770. unsigned int txbds_processed = 0;
  771. struct bcm_sysport_cb *cb;
  772. unsigned int txbds_ready;
  773. unsigned int c_index;
  774. u32 hw_ind;
  775. /* Clear status before servicing to reduce spurious interrupts */
  776. if (!ring->priv->is_lite)
  777. intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR);
  778. else
  779. intrl2_0_writel(ring->priv, BIT(ring->index +
  780. INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR);
  781. /* Compute how many descriptors have been processed since last call */
  782. hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
  783. c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
  784. txbds_ready = (c_index - ring->c_index) & RING_CONS_INDEX_MASK;
  785. netif_dbg(priv, tx_done, ndev,
  786. "ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
  787. ring->index, ring->c_index, c_index, txbds_ready);
  788. while (txbds_processed < txbds_ready) {
  789. cb = &ring->cbs[ring->clean_index];
  790. bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl);
  791. ring->desc_count++;
  792. txbds_processed++;
  793. if (likely(ring->clean_index < ring->size - 1))
  794. ring->clean_index++;
  795. else
  796. ring->clean_index = 0;
  797. }
  798. u64_stats_update_begin(&priv->syncp);
  799. ring->packets += pkts_compl;
  800. ring->bytes += bytes_compl;
  801. u64_stats_update_end(&priv->syncp);
  802. ring->c_index = c_index;
  803. netif_dbg(priv, tx_done, ndev,
  804. "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
  805. ring->index, ring->c_index, pkts_compl, bytes_compl);
  806. return pkts_compl;
  807. }
  808. /* Locked version of the per-ring TX reclaim routine */
  809. static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
  810. struct bcm_sysport_tx_ring *ring)
  811. {
  812. struct netdev_queue *txq;
  813. unsigned int released;
  814. unsigned long flags;
  815. txq = netdev_get_tx_queue(priv->netdev, ring->index);
  816. spin_lock_irqsave(&ring->lock, flags);
  817. released = __bcm_sysport_tx_reclaim(priv, ring);
  818. if (released)
  819. netif_tx_wake_queue(txq);
  820. spin_unlock_irqrestore(&ring->lock, flags);
  821. return released;
  822. }
  823. /* Locked version of the per-ring TX reclaim, but does not wake the queue */
  824. static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv,
  825. struct bcm_sysport_tx_ring *ring)
  826. {
  827. unsigned long flags;
  828. spin_lock_irqsave(&ring->lock, flags);
  829. __bcm_sysport_tx_reclaim(priv, ring);
  830. spin_unlock_irqrestore(&ring->lock, flags);
  831. }
  832. static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
  833. {
  834. struct bcm_sysport_tx_ring *ring =
  835. container_of(napi, struct bcm_sysport_tx_ring, napi);
  836. unsigned int work_done = 0;
  837. work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
  838. if (work_done == 0) {
  839. napi_complete(napi);
  840. /* re-enable TX interrupt */
  841. if (!ring->priv->is_lite)
  842. intrl2_1_mask_clear(ring->priv, BIT(ring->index));
  843. else
  844. intrl2_0_mask_clear(ring->priv, BIT(ring->index +
  845. INTRL2_0_TDMA_MBDONE_SHIFT));
  846. return 0;
  847. }
  848. return budget;
  849. }
  850. static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
  851. {
  852. unsigned int q;
  853. for (q = 0; q < priv->netdev->num_tx_queues; q++)
  854. bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
  855. }
  856. static int bcm_sysport_poll(struct napi_struct *napi, int budget)
  857. {
  858. struct bcm_sysport_priv *priv =
  859. container_of(napi, struct bcm_sysport_priv, napi);
  860. struct net_dim_sample dim_sample;
  861. unsigned int work_done = 0;
  862. work_done = bcm_sysport_desc_rx(priv, budget);
  863. priv->rx_c_index += work_done;
  864. priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
  865. /* SYSTEMPORT Lite groups the producer/consumer index, producer is
  866. * maintained by HW, but writes to it will be ignore while RDMA
  867. * is active
  868. */
  869. if (!priv->is_lite)
  870. rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
  871. else
  872. rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX);
  873. if (work_done < budget) {
  874. napi_complete_done(napi, work_done);
  875. /* re-enable RX interrupts */
  876. intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
  877. }
  878. if (priv->dim.use_dim) {
  879. net_dim_sample(priv->dim.event_ctr, priv->dim.packets,
  880. priv->dim.bytes, &dim_sample);
  881. net_dim(&priv->dim.dim, dim_sample);
  882. }
  883. return work_done;
  884. }
  885. static void mpd_enable_set(struct bcm_sysport_priv *priv, bool enable)
  886. {
  887. u32 reg, bit;
  888. reg = umac_readl(priv, UMAC_MPD_CTRL);
  889. if (enable)
  890. reg |= MPD_EN;
  891. else
  892. reg &= ~MPD_EN;
  893. umac_writel(priv, reg, UMAC_MPD_CTRL);
  894. if (priv->is_lite)
  895. bit = RBUF_ACPI_EN_LITE;
  896. else
  897. bit = RBUF_ACPI_EN;
  898. reg = rbuf_readl(priv, RBUF_CONTROL);
  899. if (enable)
  900. reg |= bit;
  901. else
  902. reg &= ~bit;
  903. rbuf_writel(priv, reg, RBUF_CONTROL);
  904. }
  905. static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
  906. {
  907. u32 reg;
  908. /* Disable RXCHK, active filters and Broadcom tag matching */
  909. reg = rxchk_readl(priv, RXCHK_CONTROL);
  910. reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK <<
  911. RXCHK_BRCM_TAG_MATCH_SHIFT | RXCHK_EN | RXCHK_BRCM_TAG_EN);
  912. rxchk_writel(priv, reg, RXCHK_CONTROL);
  913. /* Clear the MagicPacket detection logic */
  914. mpd_enable_set(priv, false);
  915. reg = intrl2_0_readl(priv, INTRL2_CPU_STATUS);
  916. if (reg & INTRL2_0_MPD)
  917. netdev_info(priv->netdev, "Wake-on-LAN (MPD) interrupt!\n");
  918. if (reg & INTRL2_0_BRCM_MATCH_TAG) {
  919. reg = rxchk_readl(priv, RXCHK_BRCM_TAG_MATCH_STATUS) &
  920. RXCHK_BRCM_TAG_MATCH_MASK;
  921. netdev_info(priv->netdev,
  922. "Wake-on-LAN (filters 0x%02x) interrupt!\n", reg);
  923. }
  924. netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
  925. }
  926. static void bcm_sysport_dim_work(struct work_struct *work)
  927. {
  928. struct net_dim *dim = container_of(work, struct net_dim, work);
  929. struct bcm_sysport_net_dim *ndim =
  930. container_of(dim, struct bcm_sysport_net_dim, dim);
  931. struct bcm_sysport_priv *priv =
  932. container_of(ndim, struct bcm_sysport_priv, dim);
  933. struct net_dim_cq_moder cur_profile =
  934. net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
  935. bcm_sysport_set_rx_coalesce(priv, cur_profile.usec, cur_profile.pkts);
  936. dim->state = NET_DIM_START_MEASURE;
  937. }
  938. /* RX and misc interrupt routine */
  939. static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
  940. {
  941. struct net_device *dev = dev_id;
  942. struct bcm_sysport_priv *priv = netdev_priv(dev);
  943. struct bcm_sysport_tx_ring *txr;
  944. unsigned int ring, ring_bit;
  945. priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
  946. ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
  947. intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
  948. if (unlikely(priv->irq0_stat == 0)) {
  949. netdev_warn(priv->netdev, "spurious RX interrupt\n");
  950. return IRQ_NONE;
  951. }
  952. if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
  953. priv->dim.event_ctr++;
  954. if (likely(napi_schedule_prep(&priv->napi))) {
  955. /* disable RX interrupts */
  956. intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
  957. __napi_schedule_irqoff(&priv->napi);
  958. }
  959. }
  960. /* TX ring is full, perform a full reclaim since we do not know
  961. * which one would trigger this interrupt
  962. */
  963. if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
  964. bcm_sysport_tx_reclaim_all(priv);
  965. if (!priv->is_lite)
  966. goto out;
  967. for (ring = 0; ring < dev->num_tx_queues; ring++) {
  968. ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT);
  969. if (!(priv->irq0_stat & ring_bit))
  970. continue;
  971. txr = &priv->tx_rings[ring];
  972. if (likely(napi_schedule_prep(&txr->napi))) {
  973. intrl2_0_mask_set(priv, ring_bit);
  974. __napi_schedule(&txr->napi);
  975. }
  976. }
  977. out:
  978. return IRQ_HANDLED;
  979. }
  980. /* TX interrupt service routine */
  981. static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
  982. {
  983. struct net_device *dev = dev_id;
  984. struct bcm_sysport_priv *priv = netdev_priv(dev);
  985. struct bcm_sysport_tx_ring *txr;
  986. unsigned int ring;
  987. priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
  988. ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
  989. intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
  990. if (unlikely(priv->irq1_stat == 0)) {
  991. netdev_warn(priv->netdev, "spurious TX interrupt\n");
  992. return IRQ_NONE;
  993. }
  994. for (ring = 0; ring < dev->num_tx_queues; ring++) {
  995. if (!(priv->irq1_stat & BIT(ring)))
  996. continue;
  997. txr = &priv->tx_rings[ring];
  998. if (likely(napi_schedule_prep(&txr->napi))) {
  999. intrl2_1_mask_set(priv, BIT(ring));
  1000. __napi_schedule_irqoff(&txr->napi);
  1001. }
  1002. }
  1003. return IRQ_HANDLED;
  1004. }
  1005. static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
  1006. {
  1007. struct bcm_sysport_priv *priv = dev_id;
  1008. pm_wakeup_event(&priv->pdev->dev, 0);
  1009. return IRQ_HANDLED;
  1010. }
  1011. #ifdef CONFIG_NET_POLL_CONTROLLER
  1012. static void bcm_sysport_poll_controller(struct net_device *dev)
  1013. {
  1014. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1015. disable_irq(priv->irq0);
  1016. bcm_sysport_rx_isr(priv->irq0, priv);
  1017. enable_irq(priv->irq0);
  1018. if (!priv->is_lite) {
  1019. disable_irq(priv->irq1);
  1020. bcm_sysport_tx_isr(priv->irq1, priv);
  1021. enable_irq(priv->irq1);
  1022. }
  1023. }
  1024. #endif
  1025. static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
  1026. struct net_device *dev)
  1027. {
  1028. struct sk_buff *nskb;
  1029. struct bcm_tsb *tsb;
  1030. u32 csum_info;
  1031. u8 ip_proto;
  1032. u16 csum_start;
  1033. __be16 ip_ver;
  1034. /* Re-allocate SKB if needed */
  1035. if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
  1036. nskb = skb_realloc_headroom(skb, sizeof(*tsb));
  1037. dev_kfree_skb(skb);
  1038. if (!nskb) {
  1039. dev->stats.tx_errors++;
  1040. dev->stats.tx_dropped++;
  1041. return NULL;
  1042. }
  1043. skb = nskb;
  1044. }
  1045. tsb = skb_push(skb, sizeof(*tsb));
  1046. /* Zero-out TSB by default */
  1047. memset(tsb, 0, sizeof(*tsb));
  1048. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1049. ip_ver = skb->protocol;
  1050. switch (ip_ver) {
  1051. case htons(ETH_P_IP):
  1052. ip_proto = ip_hdr(skb)->protocol;
  1053. break;
  1054. case htons(ETH_P_IPV6):
  1055. ip_proto = ipv6_hdr(skb)->nexthdr;
  1056. break;
  1057. default:
  1058. return skb;
  1059. }
  1060. /* Get the checksum offset and the L4 (transport) offset */
  1061. csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
  1062. csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
  1063. csum_info |= (csum_start << L4_PTR_SHIFT);
  1064. if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
  1065. csum_info |= L4_LENGTH_VALID;
  1066. if (ip_proto == IPPROTO_UDP &&
  1067. ip_ver == htons(ETH_P_IP))
  1068. csum_info |= L4_UDP;
  1069. } else {
  1070. csum_info = 0;
  1071. }
  1072. tsb->l4_ptr_dest_map = csum_info;
  1073. }
  1074. return skb;
  1075. }
  1076. static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
  1077. struct net_device *dev)
  1078. {
  1079. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1080. struct device *kdev = &priv->pdev->dev;
  1081. struct bcm_sysport_tx_ring *ring;
  1082. struct bcm_sysport_cb *cb;
  1083. struct netdev_queue *txq;
  1084. struct dma_desc *desc;
  1085. unsigned int skb_len;
  1086. unsigned long flags;
  1087. dma_addr_t mapping;
  1088. u32 len_status;
  1089. u16 queue;
  1090. int ret;
  1091. queue = skb_get_queue_mapping(skb);
  1092. txq = netdev_get_tx_queue(dev, queue);
  1093. ring = &priv->tx_rings[queue];
  1094. /* lock against tx reclaim in BH context and TX ring full interrupt */
  1095. spin_lock_irqsave(&ring->lock, flags);
  1096. if (unlikely(ring->desc_count == 0)) {
  1097. netif_tx_stop_queue(txq);
  1098. netdev_err(dev, "queue %d awake and ring full!\n", queue);
  1099. ret = NETDEV_TX_BUSY;
  1100. goto out;
  1101. }
  1102. /* Insert TSB and checksum infos */
  1103. if (priv->tsb_en) {
  1104. skb = bcm_sysport_insert_tsb(skb, dev);
  1105. if (!skb) {
  1106. ret = NETDEV_TX_OK;
  1107. goto out;
  1108. }
  1109. }
  1110. skb_len = skb->len;
  1111. mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
  1112. if (dma_mapping_error(kdev, mapping)) {
  1113. priv->mib.tx_dma_failed++;
  1114. netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
  1115. skb->data, skb_len);
  1116. ret = NETDEV_TX_OK;
  1117. goto out;
  1118. }
  1119. /* Remember the SKB for future freeing */
  1120. cb = &ring->cbs[ring->curr_desc];
  1121. cb->skb = skb;
  1122. dma_unmap_addr_set(cb, dma_addr, mapping);
  1123. dma_unmap_len_set(cb, dma_len, skb_len);
  1124. /* Fetch a descriptor entry from our pool */
  1125. desc = ring->desc_cpu;
  1126. desc->addr_lo = lower_32_bits(mapping);
  1127. len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
  1128. len_status |= (skb_len << DESC_LEN_SHIFT);
  1129. len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
  1130. DESC_STATUS_SHIFT;
  1131. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1132. len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
  1133. ring->curr_desc++;
  1134. if (ring->curr_desc == ring->size)
  1135. ring->curr_desc = 0;
  1136. ring->desc_count--;
  1137. /* Ensure write completion of the descriptor status/length
  1138. * in DRAM before the System Port WRITE_PORT register latches
  1139. * the value
  1140. */
  1141. wmb();
  1142. desc->addr_status_len = len_status;
  1143. wmb();
  1144. /* Write this descriptor address to the RING write port */
  1145. tdma_port_write_desc_addr(priv, desc, ring->index);
  1146. /* Check ring space and update SW control flow */
  1147. if (ring->desc_count == 0)
  1148. netif_tx_stop_queue(txq);
  1149. netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
  1150. ring->index, ring->desc_count, ring->curr_desc);
  1151. ret = NETDEV_TX_OK;
  1152. out:
  1153. spin_unlock_irqrestore(&ring->lock, flags);
  1154. return ret;
  1155. }
  1156. static void bcm_sysport_tx_timeout(struct net_device *dev)
  1157. {
  1158. netdev_warn(dev, "transmit timeout!\n");
  1159. netif_trans_update(dev);
  1160. dev->stats.tx_errors++;
  1161. netif_tx_wake_all_queues(dev);
  1162. }
  1163. /* phylib adjust link callback */
  1164. static void bcm_sysport_adj_link(struct net_device *dev)
  1165. {
  1166. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1167. struct phy_device *phydev = dev->phydev;
  1168. unsigned int changed = 0;
  1169. u32 cmd_bits = 0, reg;
  1170. if (priv->old_link != phydev->link) {
  1171. changed = 1;
  1172. priv->old_link = phydev->link;
  1173. }
  1174. if (priv->old_duplex != phydev->duplex) {
  1175. changed = 1;
  1176. priv->old_duplex = phydev->duplex;
  1177. }
  1178. if (priv->is_lite)
  1179. goto out;
  1180. switch (phydev->speed) {
  1181. case SPEED_2500:
  1182. cmd_bits = CMD_SPEED_2500;
  1183. break;
  1184. case SPEED_1000:
  1185. cmd_bits = CMD_SPEED_1000;
  1186. break;
  1187. case SPEED_100:
  1188. cmd_bits = CMD_SPEED_100;
  1189. break;
  1190. case SPEED_10:
  1191. cmd_bits = CMD_SPEED_10;
  1192. break;
  1193. default:
  1194. break;
  1195. }
  1196. cmd_bits <<= CMD_SPEED_SHIFT;
  1197. if (phydev->duplex == DUPLEX_HALF)
  1198. cmd_bits |= CMD_HD_EN;
  1199. if (priv->old_pause != phydev->pause) {
  1200. changed = 1;
  1201. priv->old_pause = phydev->pause;
  1202. }
  1203. if (!phydev->pause)
  1204. cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  1205. if (!changed)
  1206. return;
  1207. if (phydev->link) {
  1208. reg = umac_readl(priv, UMAC_CMD);
  1209. reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  1210. CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
  1211. CMD_TX_PAUSE_IGNORE);
  1212. reg |= cmd_bits;
  1213. umac_writel(priv, reg, UMAC_CMD);
  1214. }
  1215. out:
  1216. if (changed)
  1217. phy_print_status(phydev);
  1218. }
  1219. static void bcm_sysport_init_dim(struct bcm_sysport_priv *priv,
  1220. void (*cb)(struct work_struct *work))
  1221. {
  1222. struct bcm_sysport_net_dim *dim = &priv->dim;
  1223. INIT_WORK(&dim->dim.work, cb);
  1224. dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  1225. dim->event_ctr = 0;
  1226. dim->packets = 0;
  1227. dim->bytes = 0;
  1228. }
  1229. static void bcm_sysport_init_rx_coalesce(struct bcm_sysport_priv *priv)
  1230. {
  1231. struct bcm_sysport_net_dim *dim = &priv->dim;
  1232. struct net_dim_cq_moder moder;
  1233. u32 usecs, pkts;
  1234. usecs = priv->rx_coalesce_usecs;
  1235. pkts = priv->rx_max_coalesced_frames;
  1236. /* If DIM was enabled, re-apply default parameters */
  1237. if (dim->use_dim) {
  1238. moder = net_dim_get_def_rx_moderation(dim->dim.mode);
  1239. usecs = moder.usec;
  1240. pkts = moder.pkts;
  1241. }
  1242. bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
  1243. }
  1244. static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
  1245. unsigned int index)
  1246. {
  1247. struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
  1248. struct device *kdev = &priv->pdev->dev;
  1249. size_t size;
  1250. void *p;
  1251. u32 reg;
  1252. /* Simple descriptors partitioning for now */
  1253. size = 256;
  1254. /* We just need one DMA descriptor which is DMA-able, since writing to
  1255. * the port will allocate a new descriptor in its internal linked-list
  1256. */
  1257. p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
  1258. GFP_KERNEL);
  1259. if (!p) {
  1260. netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
  1261. return -ENOMEM;
  1262. }
  1263. ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
  1264. if (!ring->cbs) {
  1265. dma_free_coherent(kdev, sizeof(struct dma_desc),
  1266. ring->desc_cpu, ring->desc_dma);
  1267. netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
  1268. return -ENOMEM;
  1269. }
  1270. /* Initialize SW view of the ring */
  1271. spin_lock_init(&ring->lock);
  1272. ring->priv = priv;
  1273. netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
  1274. ring->index = index;
  1275. ring->size = size;
  1276. ring->clean_index = 0;
  1277. ring->alloc_size = ring->size;
  1278. ring->desc_cpu = p;
  1279. ring->desc_count = ring->size;
  1280. ring->curr_desc = 0;
  1281. /* Initialize HW ring */
  1282. tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
  1283. tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
  1284. tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
  1285. tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
  1286. /* Configure QID and port mapping */
  1287. reg = tdma_readl(priv, TDMA_DESC_RING_MAPPING(index));
  1288. reg &= ~(RING_QID_MASK | RING_PORT_ID_MASK << RING_PORT_ID_SHIFT);
  1289. if (ring->inspect) {
  1290. reg |= ring->switch_queue & RING_QID_MASK;
  1291. reg |= ring->switch_port << RING_PORT_ID_SHIFT;
  1292. } else {
  1293. reg |= RING_IGNORE_STATUS;
  1294. }
  1295. tdma_writel(priv, reg, TDMA_DESC_RING_MAPPING(index));
  1296. tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
  1297. /* Enable ACB algorithm 2 */
  1298. reg = tdma_readl(priv, TDMA_CONTROL);
  1299. reg |= tdma_control_bit(priv, ACB_ALGO);
  1300. tdma_writel(priv, reg, TDMA_CONTROL);
  1301. /* Do not use tdma_control_bit() here because TSB_SWAP1 collides
  1302. * with the original definition of ACB_ALGO
  1303. */
  1304. reg = tdma_readl(priv, TDMA_CONTROL);
  1305. if (priv->is_lite)
  1306. reg &= ~BIT(TSB_SWAP1);
  1307. /* Set a correct TSB format based on host endian */
  1308. if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  1309. reg |= tdma_control_bit(priv, TSB_SWAP0);
  1310. else
  1311. reg &= ~tdma_control_bit(priv, TSB_SWAP0);
  1312. tdma_writel(priv, reg, TDMA_CONTROL);
  1313. /* Program the number of descriptors as MAX_THRESHOLD and half of
  1314. * its size for the hysteresis trigger
  1315. */
  1316. tdma_writel(priv, ring->size |
  1317. 1 << RING_HYST_THRESH_SHIFT,
  1318. TDMA_DESC_RING_MAX_HYST(index));
  1319. /* Enable the ring queue in the arbiter */
  1320. reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
  1321. reg |= (1 << index);
  1322. tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
  1323. napi_enable(&ring->napi);
  1324. netif_dbg(priv, hw, priv->netdev,
  1325. "TDMA cfg, size=%d, desc_cpu=%p switch q=%d,port=%d\n",
  1326. ring->size, ring->desc_cpu, ring->switch_queue,
  1327. ring->switch_port);
  1328. return 0;
  1329. }
  1330. static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
  1331. unsigned int index)
  1332. {
  1333. struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
  1334. struct device *kdev = &priv->pdev->dev;
  1335. u32 reg;
  1336. /* Caller should stop the TDMA engine */
  1337. reg = tdma_readl(priv, TDMA_STATUS);
  1338. if (!(reg & TDMA_DISABLED))
  1339. netdev_warn(priv->netdev, "TDMA not stopped!\n");
  1340. /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
  1341. * fail, so by checking this pointer we know whether the TX ring was
  1342. * fully initialized or not.
  1343. */
  1344. if (!ring->cbs)
  1345. return;
  1346. napi_disable(&ring->napi);
  1347. netif_napi_del(&ring->napi);
  1348. bcm_sysport_tx_clean(priv, ring);
  1349. kfree(ring->cbs);
  1350. ring->cbs = NULL;
  1351. if (ring->desc_dma) {
  1352. dma_free_coherent(kdev, sizeof(struct dma_desc),
  1353. ring->desc_cpu, ring->desc_dma);
  1354. ring->desc_dma = 0;
  1355. }
  1356. ring->size = 0;
  1357. ring->alloc_size = 0;
  1358. netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
  1359. }
  1360. /* RDMA helper */
  1361. static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
  1362. unsigned int enable)
  1363. {
  1364. unsigned int timeout = 1000;
  1365. u32 reg;
  1366. reg = rdma_readl(priv, RDMA_CONTROL);
  1367. if (enable)
  1368. reg |= RDMA_EN;
  1369. else
  1370. reg &= ~RDMA_EN;
  1371. rdma_writel(priv, reg, RDMA_CONTROL);
  1372. /* Poll for RMDA disabling completion */
  1373. do {
  1374. reg = rdma_readl(priv, RDMA_STATUS);
  1375. if (!!(reg & RDMA_DISABLED) == !enable)
  1376. return 0;
  1377. usleep_range(1000, 2000);
  1378. } while (timeout-- > 0);
  1379. netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
  1380. return -ETIMEDOUT;
  1381. }
  1382. /* TDMA helper */
  1383. static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
  1384. unsigned int enable)
  1385. {
  1386. unsigned int timeout = 1000;
  1387. u32 reg;
  1388. reg = tdma_readl(priv, TDMA_CONTROL);
  1389. if (enable)
  1390. reg |= tdma_control_bit(priv, TDMA_EN);
  1391. else
  1392. reg &= ~tdma_control_bit(priv, TDMA_EN);
  1393. tdma_writel(priv, reg, TDMA_CONTROL);
  1394. /* Poll for TMDA disabling completion */
  1395. do {
  1396. reg = tdma_readl(priv, TDMA_STATUS);
  1397. if (!!(reg & TDMA_DISABLED) == !enable)
  1398. return 0;
  1399. usleep_range(1000, 2000);
  1400. } while (timeout-- > 0);
  1401. netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
  1402. return -ETIMEDOUT;
  1403. }
  1404. static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
  1405. {
  1406. struct bcm_sysport_cb *cb;
  1407. u32 reg;
  1408. int ret;
  1409. int i;
  1410. /* Initialize SW view of the RX ring */
  1411. priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC;
  1412. priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
  1413. priv->rx_c_index = 0;
  1414. priv->rx_read_ptr = 0;
  1415. priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
  1416. GFP_KERNEL);
  1417. if (!priv->rx_cbs) {
  1418. netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
  1419. return -ENOMEM;
  1420. }
  1421. for (i = 0; i < priv->num_rx_bds; i++) {
  1422. cb = priv->rx_cbs + i;
  1423. cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
  1424. }
  1425. ret = bcm_sysport_alloc_rx_bufs(priv);
  1426. if (ret) {
  1427. netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
  1428. return ret;
  1429. }
  1430. /* Initialize HW, ensure RDMA is disabled */
  1431. reg = rdma_readl(priv, RDMA_STATUS);
  1432. if (!(reg & RDMA_DISABLED))
  1433. rdma_enable_set(priv, 0);
  1434. rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
  1435. rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
  1436. rdma_writel(priv, 0, RDMA_PROD_INDEX);
  1437. rdma_writel(priv, 0, RDMA_CONS_INDEX);
  1438. rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
  1439. RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
  1440. /* Operate the queue in ring mode */
  1441. rdma_writel(priv, 0, RDMA_START_ADDR_HI);
  1442. rdma_writel(priv, 0, RDMA_START_ADDR_LO);
  1443. rdma_writel(priv, 0, RDMA_END_ADDR_HI);
  1444. rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO);
  1445. netif_dbg(priv, hw, priv->netdev,
  1446. "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
  1447. priv->num_rx_bds, priv->rx_bds);
  1448. return 0;
  1449. }
  1450. static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
  1451. {
  1452. struct bcm_sysport_cb *cb;
  1453. unsigned int i;
  1454. u32 reg;
  1455. /* Caller should ensure RDMA is disabled */
  1456. reg = rdma_readl(priv, RDMA_STATUS);
  1457. if (!(reg & RDMA_DISABLED))
  1458. netdev_warn(priv->netdev, "RDMA not stopped!\n");
  1459. for (i = 0; i < priv->num_rx_bds; i++) {
  1460. cb = &priv->rx_cbs[i];
  1461. if (dma_unmap_addr(cb, dma_addr))
  1462. dma_unmap_single(&priv->pdev->dev,
  1463. dma_unmap_addr(cb, dma_addr),
  1464. RX_BUF_LENGTH, DMA_FROM_DEVICE);
  1465. bcm_sysport_free_cb(cb);
  1466. }
  1467. kfree(priv->rx_cbs);
  1468. priv->rx_cbs = NULL;
  1469. netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
  1470. }
  1471. static void bcm_sysport_set_rx_mode(struct net_device *dev)
  1472. {
  1473. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1474. u32 reg;
  1475. if (priv->is_lite)
  1476. return;
  1477. reg = umac_readl(priv, UMAC_CMD);
  1478. if (dev->flags & IFF_PROMISC)
  1479. reg |= CMD_PROMISC;
  1480. else
  1481. reg &= ~CMD_PROMISC;
  1482. umac_writel(priv, reg, UMAC_CMD);
  1483. /* No support for ALLMULTI */
  1484. if (dev->flags & IFF_ALLMULTI)
  1485. return;
  1486. }
  1487. static inline void umac_enable_set(struct bcm_sysport_priv *priv,
  1488. u32 mask, unsigned int enable)
  1489. {
  1490. u32 reg;
  1491. if (!priv->is_lite) {
  1492. reg = umac_readl(priv, UMAC_CMD);
  1493. if (enable)
  1494. reg |= mask;
  1495. else
  1496. reg &= ~mask;
  1497. umac_writel(priv, reg, UMAC_CMD);
  1498. } else {
  1499. reg = gib_readl(priv, GIB_CONTROL);
  1500. if (enable)
  1501. reg |= mask;
  1502. else
  1503. reg &= ~mask;
  1504. gib_writel(priv, reg, GIB_CONTROL);
  1505. }
  1506. /* UniMAC stops on a packet boundary, wait for a full-sized packet
  1507. * to be processed (1 msec).
  1508. */
  1509. if (enable == 0)
  1510. usleep_range(1000, 2000);
  1511. }
  1512. static inline void umac_reset(struct bcm_sysport_priv *priv)
  1513. {
  1514. u32 reg;
  1515. if (priv->is_lite)
  1516. return;
  1517. reg = umac_readl(priv, UMAC_CMD);
  1518. reg |= CMD_SW_RESET;
  1519. umac_writel(priv, reg, UMAC_CMD);
  1520. udelay(10);
  1521. reg = umac_readl(priv, UMAC_CMD);
  1522. reg &= ~CMD_SW_RESET;
  1523. umac_writel(priv, reg, UMAC_CMD);
  1524. }
  1525. static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
  1526. unsigned char *addr)
  1527. {
  1528. u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
  1529. addr[3];
  1530. u32 mac1 = (addr[4] << 8) | addr[5];
  1531. if (!priv->is_lite) {
  1532. umac_writel(priv, mac0, UMAC_MAC0);
  1533. umac_writel(priv, mac1, UMAC_MAC1);
  1534. } else {
  1535. gib_writel(priv, mac0, GIB_MAC0);
  1536. gib_writel(priv, mac1, GIB_MAC1);
  1537. }
  1538. }
  1539. static void topctrl_flush(struct bcm_sysport_priv *priv)
  1540. {
  1541. topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
  1542. topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
  1543. mdelay(1);
  1544. topctrl_writel(priv, 0, RX_FLUSH_CNTL);
  1545. topctrl_writel(priv, 0, TX_FLUSH_CNTL);
  1546. }
  1547. static int bcm_sysport_change_mac(struct net_device *dev, void *p)
  1548. {
  1549. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1550. struct sockaddr *addr = p;
  1551. if (!is_valid_ether_addr(addr->sa_data))
  1552. return -EINVAL;
  1553. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  1554. /* interface is disabled, changes to MAC will be reflected on next
  1555. * open call
  1556. */
  1557. if (!netif_running(dev))
  1558. return 0;
  1559. umac_set_hw_addr(priv, dev->dev_addr);
  1560. return 0;
  1561. }
  1562. static void bcm_sysport_get_stats64(struct net_device *dev,
  1563. struct rtnl_link_stats64 *stats)
  1564. {
  1565. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1566. struct bcm_sysport_stats64 *stats64 = &priv->stats64;
  1567. unsigned int start;
  1568. netdev_stats_to_stats64(stats, &dev->stats);
  1569. bcm_sysport_update_tx_stats(priv, &stats->tx_bytes,
  1570. &stats->tx_packets);
  1571. do {
  1572. start = u64_stats_fetch_begin_irq(&priv->syncp);
  1573. stats->rx_packets = stats64->rx_packets;
  1574. stats->rx_bytes = stats64->rx_bytes;
  1575. } while (u64_stats_fetch_retry_irq(&priv->syncp, start));
  1576. }
  1577. static void bcm_sysport_netif_start(struct net_device *dev)
  1578. {
  1579. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1580. /* Enable NAPI */
  1581. bcm_sysport_init_dim(priv, bcm_sysport_dim_work);
  1582. bcm_sysport_init_rx_coalesce(priv);
  1583. napi_enable(&priv->napi);
  1584. /* Enable RX interrupt and TX ring full interrupt */
  1585. intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
  1586. phy_start(dev->phydev);
  1587. /* Enable TX interrupts for the TXQs */
  1588. if (!priv->is_lite)
  1589. intrl2_1_mask_clear(priv, 0xffffffff);
  1590. else
  1591. intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK);
  1592. }
  1593. static void rbuf_init(struct bcm_sysport_priv *priv)
  1594. {
  1595. u32 reg;
  1596. reg = rbuf_readl(priv, RBUF_CONTROL);
  1597. reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
  1598. /* Set a correct RSB format on SYSTEMPORT Lite */
  1599. if (priv->is_lite)
  1600. reg &= ~RBUF_RSB_SWAP1;
  1601. /* Set a correct RSB format based on host endian */
  1602. if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  1603. reg |= RBUF_RSB_SWAP0;
  1604. else
  1605. reg &= ~RBUF_RSB_SWAP0;
  1606. rbuf_writel(priv, reg, RBUF_CONTROL);
  1607. }
  1608. static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv)
  1609. {
  1610. intrl2_0_mask_set(priv, 0xffffffff);
  1611. intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
  1612. if (!priv->is_lite) {
  1613. intrl2_1_mask_set(priv, 0xffffffff);
  1614. intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
  1615. }
  1616. }
  1617. static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv)
  1618. {
  1619. u32 reg;
  1620. reg = gib_readl(priv, GIB_CONTROL);
  1621. /* Include Broadcom tag in pad extension and fix up IPG_LENGTH */
  1622. if (netdev_uses_dsa(priv->netdev)) {
  1623. reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT);
  1624. reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT;
  1625. }
  1626. reg &= ~(GIB_IPG_LEN_MASK << GIB_IPG_LEN_SHIFT);
  1627. reg |= 12 << GIB_IPG_LEN_SHIFT;
  1628. gib_writel(priv, reg, GIB_CONTROL);
  1629. }
  1630. static int bcm_sysport_open(struct net_device *dev)
  1631. {
  1632. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1633. struct phy_device *phydev;
  1634. unsigned int i;
  1635. int ret;
  1636. /* Reset UniMAC */
  1637. umac_reset(priv);
  1638. /* Flush TX and RX FIFOs at TOPCTRL level */
  1639. topctrl_flush(priv);
  1640. /* Disable the UniMAC RX/TX */
  1641. umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
  1642. /* Enable RBUF 2bytes alignment and Receive Status Block */
  1643. rbuf_init(priv);
  1644. /* Set maximum frame length */
  1645. if (!priv->is_lite)
  1646. umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
  1647. else
  1648. gib_set_pad_extension(priv);
  1649. /* Set MAC address */
  1650. umac_set_hw_addr(priv, dev->dev_addr);
  1651. /* Read CRC forward */
  1652. if (!priv->is_lite)
  1653. priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
  1654. else
  1655. priv->crc_fwd = !((gib_readl(priv, GIB_CONTROL) &
  1656. GIB_FCS_STRIP) >> GIB_FCS_STRIP_SHIFT);
  1657. phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
  1658. 0, priv->phy_interface);
  1659. if (!phydev) {
  1660. netdev_err(dev, "could not attach to PHY\n");
  1661. return -ENODEV;
  1662. }
  1663. /* Reset house keeping link status */
  1664. priv->old_duplex = -1;
  1665. priv->old_link = -1;
  1666. priv->old_pause = -1;
  1667. /* mask all interrupts and request them */
  1668. bcm_sysport_mask_all_intrs(priv);
  1669. ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
  1670. if (ret) {
  1671. netdev_err(dev, "failed to request RX interrupt\n");
  1672. goto out_phy_disconnect;
  1673. }
  1674. if (!priv->is_lite) {
  1675. ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0,
  1676. dev->name, dev);
  1677. if (ret) {
  1678. netdev_err(dev, "failed to request TX interrupt\n");
  1679. goto out_free_irq0;
  1680. }
  1681. }
  1682. /* Initialize both hardware and software ring */
  1683. for (i = 0; i < dev->num_tx_queues; i++) {
  1684. ret = bcm_sysport_init_tx_ring(priv, i);
  1685. if (ret) {
  1686. netdev_err(dev, "failed to initialize TX ring %d\n",
  1687. i);
  1688. goto out_free_tx_ring;
  1689. }
  1690. }
  1691. /* Initialize linked-list */
  1692. tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
  1693. /* Initialize RX ring */
  1694. ret = bcm_sysport_init_rx_ring(priv);
  1695. if (ret) {
  1696. netdev_err(dev, "failed to initialize RX ring\n");
  1697. goto out_free_rx_ring;
  1698. }
  1699. /* Turn on RDMA */
  1700. ret = rdma_enable_set(priv, 1);
  1701. if (ret)
  1702. goto out_free_rx_ring;
  1703. /* Turn on TDMA */
  1704. ret = tdma_enable_set(priv, 1);
  1705. if (ret)
  1706. goto out_clear_rx_int;
  1707. /* Turn on UniMAC TX/RX */
  1708. umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
  1709. bcm_sysport_netif_start(dev);
  1710. netif_tx_start_all_queues(dev);
  1711. return 0;
  1712. out_clear_rx_int:
  1713. intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
  1714. out_free_rx_ring:
  1715. bcm_sysport_fini_rx_ring(priv);
  1716. out_free_tx_ring:
  1717. for (i = 0; i < dev->num_tx_queues; i++)
  1718. bcm_sysport_fini_tx_ring(priv, i);
  1719. if (!priv->is_lite)
  1720. free_irq(priv->irq1, dev);
  1721. out_free_irq0:
  1722. free_irq(priv->irq0, dev);
  1723. out_phy_disconnect:
  1724. phy_disconnect(phydev);
  1725. return ret;
  1726. }
  1727. static void bcm_sysport_netif_stop(struct net_device *dev)
  1728. {
  1729. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1730. /* stop all software from updating hardware */
  1731. netif_tx_disable(dev);
  1732. napi_disable(&priv->napi);
  1733. cancel_work_sync(&priv->dim.dim.work);
  1734. phy_stop(dev->phydev);
  1735. /* mask all interrupts */
  1736. bcm_sysport_mask_all_intrs(priv);
  1737. }
  1738. static int bcm_sysport_stop(struct net_device *dev)
  1739. {
  1740. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1741. unsigned int i;
  1742. int ret;
  1743. bcm_sysport_netif_stop(dev);
  1744. /* Disable UniMAC RX */
  1745. umac_enable_set(priv, CMD_RX_EN, 0);
  1746. ret = tdma_enable_set(priv, 0);
  1747. if (ret) {
  1748. netdev_err(dev, "timeout disabling RDMA\n");
  1749. return ret;
  1750. }
  1751. /* Wait for a maximum packet size to be drained */
  1752. usleep_range(2000, 3000);
  1753. ret = rdma_enable_set(priv, 0);
  1754. if (ret) {
  1755. netdev_err(dev, "timeout disabling TDMA\n");
  1756. return ret;
  1757. }
  1758. /* Disable UniMAC TX */
  1759. umac_enable_set(priv, CMD_TX_EN, 0);
  1760. /* Free RX/TX rings SW structures */
  1761. for (i = 0; i < dev->num_tx_queues; i++)
  1762. bcm_sysport_fini_tx_ring(priv, i);
  1763. bcm_sysport_fini_rx_ring(priv);
  1764. free_irq(priv->irq0, dev);
  1765. if (!priv->is_lite)
  1766. free_irq(priv->irq1, dev);
  1767. /* Disconnect from PHY */
  1768. phy_disconnect(dev->phydev);
  1769. return 0;
  1770. }
  1771. static int bcm_sysport_rule_find(struct bcm_sysport_priv *priv,
  1772. u64 location)
  1773. {
  1774. unsigned int index;
  1775. u32 reg;
  1776. for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
  1777. reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index));
  1778. reg >>= RXCHK_BRCM_TAG_CID_SHIFT;
  1779. reg &= RXCHK_BRCM_TAG_CID_MASK;
  1780. if (reg == location)
  1781. return index;
  1782. }
  1783. return -EINVAL;
  1784. }
  1785. static int bcm_sysport_rule_get(struct bcm_sysport_priv *priv,
  1786. struct ethtool_rxnfc *nfc)
  1787. {
  1788. int index;
  1789. /* This is not a rule that we know about */
  1790. index = bcm_sysport_rule_find(priv, nfc->fs.location);
  1791. if (index < 0)
  1792. return -EOPNOTSUPP;
  1793. nfc->fs.ring_cookie = RX_CLS_FLOW_WAKE;
  1794. return 0;
  1795. }
  1796. static int bcm_sysport_rule_set(struct bcm_sysport_priv *priv,
  1797. struct ethtool_rxnfc *nfc)
  1798. {
  1799. unsigned int index;
  1800. u32 reg;
  1801. /* We cannot match locations greater than what the classification ID
  1802. * permits (256 entries)
  1803. */
  1804. if (nfc->fs.location > RXCHK_BRCM_TAG_CID_MASK)
  1805. return -E2BIG;
  1806. /* We cannot support flows that are not destined for a wake-up */
  1807. if (nfc->fs.ring_cookie != RX_CLS_FLOW_WAKE)
  1808. return -EOPNOTSUPP;
  1809. /* All filters are already in use, we cannot match more rules */
  1810. if (bitmap_weight(priv->filters, RXCHK_BRCM_TAG_MAX) ==
  1811. RXCHK_BRCM_TAG_MAX)
  1812. return -ENOSPC;
  1813. index = find_first_zero_bit(priv->filters, RXCHK_BRCM_TAG_MAX);
  1814. if (index >= RXCHK_BRCM_TAG_MAX)
  1815. return -ENOSPC;
  1816. /* Location is the classification ID, and index is the position
  1817. * within one of our 8 possible filters to be programmed
  1818. */
  1819. reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index));
  1820. reg &= ~(RXCHK_BRCM_TAG_CID_MASK << RXCHK_BRCM_TAG_CID_SHIFT);
  1821. reg |= nfc->fs.location << RXCHK_BRCM_TAG_CID_SHIFT;
  1822. rxchk_writel(priv, reg, RXCHK_BRCM_TAG(index));
  1823. rxchk_writel(priv, 0xff00ffff, RXCHK_BRCM_TAG_MASK(index));
  1824. set_bit(index, priv->filters);
  1825. return 0;
  1826. }
  1827. static int bcm_sysport_rule_del(struct bcm_sysport_priv *priv,
  1828. u64 location)
  1829. {
  1830. int index;
  1831. /* This is not a rule that we know about */
  1832. index = bcm_sysport_rule_find(priv, location);
  1833. if (index < 0)
  1834. return -EOPNOTSUPP;
  1835. /* No need to disable this filter if it was enabled, this will
  1836. * be taken care of during suspend time by bcm_sysport_suspend_to_wol
  1837. */
  1838. clear_bit(index, priv->filters);
  1839. return 0;
  1840. }
  1841. static int bcm_sysport_get_rxnfc(struct net_device *dev,
  1842. struct ethtool_rxnfc *nfc, u32 *rule_locs)
  1843. {
  1844. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1845. int ret = -EOPNOTSUPP;
  1846. switch (nfc->cmd) {
  1847. case ETHTOOL_GRXCLSRULE:
  1848. ret = bcm_sysport_rule_get(priv, nfc);
  1849. break;
  1850. default:
  1851. break;
  1852. }
  1853. return ret;
  1854. }
  1855. static int bcm_sysport_set_rxnfc(struct net_device *dev,
  1856. struct ethtool_rxnfc *nfc)
  1857. {
  1858. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1859. int ret = -EOPNOTSUPP;
  1860. switch (nfc->cmd) {
  1861. case ETHTOOL_SRXCLSRLINS:
  1862. ret = bcm_sysport_rule_set(priv, nfc);
  1863. break;
  1864. case ETHTOOL_SRXCLSRLDEL:
  1865. ret = bcm_sysport_rule_del(priv, nfc->fs.location);
  1866. break;
  1867. default:
  1868. break;
  1869. }
  1870. return ret;
  1871. }
  1872. static const struct ethtool_ops bcm_sysport_ethtool_ops = {
  1873. .get_drvinfo = bcm_sysport_get_drvinfo,
  1874. .get_msglevel = bcm_sysport_get_msglvl,
  1875. .set_msglevel = bcm_sysport_set_msglvl,
  1876. .get_link = ethtool_op_get_link,
  1877. .get_strings = bcm_sysport_get_strings,
  1878. .get_ethtool_stats = bcm_sysport_get_stats,
  1879. .get_sset_count = bcm_sysport_get_sset_count,
  1880. .get_wol = bcm_sysport_get_wol,
  1881. .set_wol = bcm_sysport_set_wol,
  1882. .get_coalesce = bcm_sysport_get_coalesce,
  1883. .set_coalesce = bcm_sysport_set_coalesce,
  1884. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  1885. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  1886. .get_rxnfc = bcm_sysport_get_rxnfc,
  1887. .set_rxnfc = bcm_sysport_set_rxnfc,
  1888. };
  1889. static u16 bcm_sysport_select_queue(struct net_device *dev, struct sk_buff *skb,
  1890. struct net_device *sb_dev,
  1891. select_queue_fallback_t fallback)
  1892. {
  1893. struct bcm_sysport_priv *priv = netdev_priv(dev);
  1894. u16 queue = skb_get_queue_mapping(skb);
  1895. struct bcm_sysport_tx_ring *tx_ring;
  1896. unsigned int q, port;
  1897. if (!netdev_uses_dsa(dev))
  1898. return fallback(dev, skb, NULL);
  1899. /* DSA tagging layer will have configured the correct queue */
  1900. q = BRCM_TAG_GET_QUEUE(queue);
  1901. port = BRCM_TAG_GET_PORT(queue);
  1902. tx_ring = priv->ring_map[q + port * priv->per_port_num_tx_queues];
  1903. if (unlikely(!tx_ring))
  1904. return fallback(dev, skb, NULL);
  1905. return tx_ring->index;
  1906. }
  1907. static const struct net_device_ops bcm_sysport_netdev_ops = {
  1908. .ndo_start_xmit = bcm_sysport_xmit,
  1909. .ndo_tx_timeout = bcm_sysport_tx_timeout,
  1910. .ndo_open = bcm_sysport_open,
  1911. .ndo_stop = bcm_sysport_stop,
  1912. .ndo_set_features = bcm_sysport_set_features,
  1913. .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
  1914. .ndo_set_mac_address = bcm_sysport_change_mac,
  1915. #ifdef CONFIG_NET_POLL_CONTROLLER
  1916. .ndo_poll_controller = bcm_sysport_poll_controller,
  1917. #endif
  1918. .ndo_get_stats64 = bcm_sysport_get_stats64,
  1919. .ndo_select_queue = bcm_sysport_select_queue,
  1920. };
  1921. static int bcm_sysport_map_queues(struct notifier_block *nb,
  1922. struct dsa_notifier_register_info *info)
  1923. {
  1924. struct bcm_sysport_tx_ring *ring;
  1925. struct bcm_sysport_priv *priv;
  1926. struct net_device *slave_dev;
  1927. unsigned int num_tx_queues;
  1928. unsigned int q, start, port;
  1929. struct net_device *dev;
  1930. priv = container_of(nb, struct bcm_sysport_priv, dsa_notifier);
  1931. if (priv->netdev != info->master)
  1932. return 0;
  1933. dev = info->master;
  1934. /* We can't be setting up queue inspection for non directly attached
  1935. * switches
  1936. */
  1937. if (info->switch_number)
  1938. return 0;
  1939. if (dev->netdev_ops != &bcm_sysport_netdev_ops)
  1940. return 0;
  1941. port = info->port_number;
  1942. slave_dev = info->info.dev;
  1943. /* On SYSTEMPORT Lite we have twice as less queues, so we cannot do a
  1944. * 1:1 mapping, we can only do a 2:1 mapping. By reducing the number of
  1945. * per-port (slave_dev) network devices queue, we achieve just that.
  1946. * This need to happen now before any slave network device is used such
  1947. * it accurately reflects the number of real TX queues.
  1948. */
  1949. if (priv->is_lite)
  1950. netif_set_real_num_tx_queues(slave_dev,
  1951. slave_dev->num_tx_queues / 2);
  1952. num_tx_queues = slave_dev->real_num_tx_queues;
  1953. if (priv->per_port_num_tx_queues &&
  1954. priv->per_port_num_tx_queues != num_tx_queues)
  1955. netdev_warn(slave_dev, "asymmetric number of per-port queues\n");
  1956. priv->per_port_num_tx_queues = num_tx_queues;
  1957. start = find_first_zero_bit(&priv->queue_bitmap, dev->num_tx_queues);
  1958. for (q = 0; q < num_tx_queues; q++) {
  1959. ring = &priv->tx_rings[q + start];
  1960. /* Just remember the mapping actual programming done
  1961. * during bcm_sysport_init_tx_ring
  1962. */
  1963. ring->switch_queue = q;
  1964. ring->switch_port = port;
  1965. ring->inspect = true;
  1966. priv->ring_map[q + port * num_tx_queues] = ring;
  1967. /* Set all queues as being used now */
  1968. set_bit(q + start, &priv->queue_bitmap);
  1969. }
  1970. return 0;
  1971. }
  1972. static int bcm_sysport_dsa_notifier(struct notifier_block *nb,
  1973. unsigned long event, void *ptr)
  1974. {
  1975. struct dsa_notifier_register_info *info;
  1976. if (event != DSA_PORT_REGISTER)
  1977. return NOTIFY_DONE;
  1978. info = ptr;
  1979. return notifier_from_errno(bcm_sysport_map_queues(nb, info));
  1980. }
  1981. #define REV_FMT "v%2x.%02x"
  1982. static const struct bcm_sysport_hw_params bcm_sysport_params[] = {
  1983. [SYSTEMPORT] = {
  1984. .is_lite = false,
  1985. .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS,
  1986. },
  1987. [SYSTEMPORT_LITE] = {
  1988. .is_lite = true,
  1989. .num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS,
  1990. },
  1991. };
  1992. static const struct of_device_id bcm_sysport_of_match[] = {
  1993. { .compatible = "brcm,systemportlite-v1.00",
  1994. .data = &bcm_sysport_params[SYSTEMPORT_LITE] },
  1995. { .compatible = "brcm,systemport-v1.00",
  1996. .data = &bcm_sysport_params[SYSTEMPORT] },
  1997. { .compatible = "brcm,systemport",
  1998. .data = &bcm_sysport_params[SYSTEMPORT] },
  1999. { /* sentinel */ }
  2000. };
  2001. MODULE_DEVICE_TABLE(of, bcm_sysport_of_match);
  2002. static int bcm_sysport_probe(struct platform_device *pdev)
  2003. {
  2004. const struct bcm_sysport_hw_params *params;
  2005. const struct of_device_id *of_id = NULL;
  2006. struct bcm_sysport_priv *priv;
  2007. struct device_node *dn;
  2008. struct net_device *dev;
  2009. const void *macaddr;
  2010. struct resource *r;
  2011. u32 txq, rxq;
  2012. int ret;
  2013. dn = pdev->dev.of_node;
  2014. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2015. of_id = of_match_node(bcm_sysport_of_match, dn);
  2016. if (!of_id || !of_id->data)
  2017. return -EINVAL;
  2018. /* Fairly quickly we need to know the type of adapter we have */
  2019. params = of_id->data;
  2020. /* Read the Transmit/Receive Queue properties */
  2021. if (of_property_read_u32(dn, "systemport,num-txq", &txq))
  2022. txq = TDMA_NUM_RINGS;
  2023. if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
  2024. rxq = 1;
  2025. /* Sanity check the number of transmit queues */
  2026. if (!txq || txq > TDMA_NUM_RINGS)
  2027. return -EINVAL;
  2028. dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
  2029. if (!dev)
  2030. return -ENOMEM;
  2031. /* Initialize private members */
  2032. priv = netdev_priv(dev);
  2033. /* Allocate number of TX rings */
  2034. priv->tx_rings = devm_kcalloc(&pdev->dev, txq,
  2035. sizeof(struct bcm_sysport_tx_ring),
  2036. GFP_KERNEL);
  2037. if (!priv->tx_rings) {
  2038. ret = -ENOMEM;
  2039. goto err_free_netdev;
  2040. }
  2041. priv->is_lite = params->is_lite;
  2042. priv->num_rx_desc_words = params->num_rx_desc_words;
  2043. priv->irq0 = platform_get_irq(pdev, 0);
  2044. if (!priv->is_lite) {
  2045. priv->irq1 = platform_get_irq(pdev, 1);
  2046. priv->wol_irq = platform_get_irq(pdev, 2);
  2047. } else {
  2048. priv->wol_irq = platform_get_irq(pdev, 1);
  2049. }
  2050. if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) {
  2051. dev_err(&pdev->dev, "invalid interrupts\n");
  2052. ret = -EINVAL;
  2053. goto err_free_netdev;
  2054. }
  2055. priv->base = devm_ioremap_resource(&pdev->dev, r);
  2056. if (IS_ERR(priv->base)) {
  2057. ret = PTR_ERR(priv->base);
  2058. goto err_free_netdev;
  2059. }
  2060. priv->netdev = dev;
  2061. priv->pdev = pdev;
  2062. priv->phy_interface = of_get_phy_mode(dn);
  2063. /* Default to GMII interface mode */
  2064. if ((int)priv->phy_interface < 0)
  2065. priv->phy_interface = PHY_INTERFACE_MODE_GMII;
  2066. /* In the case of a fixed PHY, the DT node associated
  2067. * to the PHY is the Ethernet MAC DT node.
  2068. */
  2069. if (of_phy_is_fixed_link(dn)) {
  2070. ret = of_phy_register_fixed_link(dn);
  2071. if (ret) {
  2072. dev_err(&pdev->dev, "failed to register fixed PHY\n");
  2073. goto err_free_netdev;
  2074. }
  2075. priv->phy_dn = dn;
  2076. }
  2077. /* Initialize netdevice members */
  2078. macaddr = of_get_mac_address(dn);
  2079. if (!macaddr || !is_valid_ether_addr(macaddr)) {
  2080. dev_warn(&pdev->dev, "using random Ethernet MAC\n");
  2081. eth_hw_addr_random(dev);
  2082. } else {
  2083. ether_addr_copy(dev->dev_addr, macaddr);
  2084. }
  2085. SET_NETDEV_DEV(dev, &pdev->dev);
  2086. dev_set_drvdata(&pdev->dev, dev);
  2087. dev->ethtool_ops = &bcm_sysport_ethtool_ops;
  2088. dev->netdev_ops = &bcm_sysport_netdev_ops;
  2089. netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
  2090. /* HW supported features, none enabled by default */
  2091. dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
  2092. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  2093. dev->max_mtu = UMAC_MAX_MTU_SIZE;
  2094. /* Request the WOL interrupt and advertise suspend if available */
  2095. priv->wol_irq_disabled = 1;
  2096. ret = devm_request_irq(&pdev->dev, priv->wol_irq,
  2097. bcm_sysport_wol_isr, 0, dev->name, priv);
  2098. if (!ret)
  2099. device_set_wakeup_capable(&pdev->dev, 1);
  2100. /* Set the needed headroom once and for all */
  2101. BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
  2102. dev->needed_headroom += sizeof(struct bcm_tsb);
  2103. /* libphy will adjust the link state accordingly */
  2104. netif_carrier_off(dev);
  2105. priv->rx_max_coalesced_frames = 1;
  2106. u64_stats_init(&priv->syncp);
  2107. priv->dsa_notifier.notifier_call = bcm_sysport_dsa_notifier;
  2108. ret = register_dsa_notifier(&priv->dsa_notifier);
  2109. if (ret) {
  2110. dev_err(&pdev->dev, "failed to register DSA notifier\n");
  2111. goto err_deregister_fixed_link;
  2112. }
  2113. ret = register_netdev(dev);
  2114. if (ret) {
  2115. dev_err(&pdev->dev, "failed to register net_device\n");
  2116. goto err_deregister_notifier;
  2117. }
  2118. priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
  2119. dev_info(&pdev->dev,
  2120. "Broadcom SYSTEMPORT%s" REV_FMT
  2121. " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
  2122. priv->is_lite ? " Lite" : "",
  2123. (priv->rev >> 8) & 0xff, priv->rev & 0xff,
  2124. priv->base, priv->irq0, priv->irq1, txq, rxq);
  2125. return 0;
  2126. err_deregister_notifier:
  2127. unregister_dsa_notifier(&priv->dsa_notifier);
  2128. err_deregister_fixed_link:
  2129. if (of_phy_is_fixed_link(dn))
  2130. of_phy_deregister_fixed_link(dn);
  2131. err_free_netdev:
  2132. free_netdev(dev);
  2133. return ret;
  2134. }
  2135. static int bcm_sysport_remove(struct platform_device *pdev)
  2136. {
  2137. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  2138. struct bcm_sysport_priv *priv = netdev_priv(dev);
  2139. struct device_node *dn = pdev->dev.of_node;
  2140. /* Not much to do, ndo_close has been called
  2141. * and we use managed allocations
  2142. */
  2143. unregister_dsa_notifier(&priv->dsa_notifier);
  2144. unregister_netdev(dev);
  2145. if (of_phy_is_fixed_link(dn))
  2146. of_phy_deregister_fixed_link(dn);
  2147. free_netdev(dev);
  2148. dev_set_drvdata(&pdev->dev, NULL);
  2149. return 0;
  2150. }
  2151. static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
  2152. {
  2153. struct net_device *ndev = priv->netdev;
  2154. unsigned int timeout = 1000;
  2155. unsigned int index, i = 0;
  2156. u32 reg;
  2157. reg = umac_readl(priv, UMAC_MPD_CTRL);
  2158. if (priv->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE))
  2159. reg |= MPD_EN;
  2160. reg &= ~PSW_EN;
  2161. if (priv->wolopts & WAKE_MAGICSECURE) {
  2162. /* Program the SecureOn password */
  2163. umac_writel(priv, get_unaligned_be16(&priv->sopass[0]),
  2164. UMAC_PSW_MS);
  2165. umac_writel(priv, get_unaligned_be32(&priv->sopass[2]),
  2166. UMAC_PSW_LS);
  2167. reg |= PSW_EN;
  2168. }
  2169. umac_writel(priv, reg, UMAC_MPD_CTRL);
  2170. if (priv->wolopts & WAKE_FILTER) {
  2171. /* Turn on ACPI matching to steal packets from RBUF */
  2172. reg = rbuf_readl(priv, RBUF_CONTROL);
  2173. if (priv->is_lite)
  2174. reg |= RBUF_ACPI_EN_LITE;
  2175. else
  2176. reg |= RBUF_ACPI_EN;
  2177. rbuf_writel(priv, reg, RBUF_CONTROL);
  2178. /* Enable RXCHK, active filters and Broadcom tag matching */
  2179. reg = rxchk_readl(priv, RXCHK_CONTROL);
  2180. reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK <<
  2181. RXCHK_BRCM_TAG_MATCH_SHIFT);
  2182. for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
  2183. reg |= BIT(RXCHK_BRCM_TAG_MATCH_SHIFT + i);
  2184. i++;
  2185. }
  2186. reg |= RXCHK_EN | RXCHK_BRCM_TAG_EN;
  2187. rxchk_writel(priv, reg, RXCHK_CONTROL);
  2188. }
  2189. /* Make sure RBUF entered WoL mode as result */
  2190. do {
  2191. reg = rbuf_readl(priv, RBUF_STATUS);
  2192. if (reg & RBUF_WOL_MODE)
  2193. break;
  2194. udelay(10);
  2195. } while (timeout-- > 0);
  2196. /* Do not leave the UniMAC RBUF matching only MPD packets */
  2197. if (!timeout) {
  2198. mpd_enable_set(priv, false);
  2199. netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
  2200. return -ETIMEDOUT;
  2201. }
  2202. /* UniMAC receive needs to be turned on */
  2203. umac_enable_set(priv, CMD_RX_EN, 1);
  2204. netif_dbg(priv, wol, ndev, "entered WOL mode\n");
  2205. return 0;
  2206. }
  2207. static int __maybe_unused bcm_sysport_suspend(struct device *d)
  2208. {
  2209. struct net_device *dev = dev_get_drvdata(d);
  2210. struct bcm_sysport_priv *priv = netdev_priv(dev);
  2211. unsigned int i;
  2212. int ret = 0;
  2213. u32 reg;
  2214. if (!netif_running(dev))
  2215. return 0;
  2216. netif_device_detach(dev);
  2217. bcm_sysport_netif_stop(dev);
  2218. phy_suspend(dev->phydev);
  2219. /* Disable UniMAC RX */
  2220. umac_enable_set(priv, CMD_RX_EN, 0);
  2221. ret = rdma_enable_set(priv, 0);
  2222. if (ret) {
  2223. netdev_err(dev, "RDMA timeout!\n");
  2224. return ret;
  2225. }
  2226. /* Disable RXCHK if enabled */
  2227. if (priv->rx_chk_en) {
  2228. reg = rxchk_readl(priv, RXCHK_CONTROL);
  2229. reg &= ~RXCHK_EN;
  2230. rxchk_writel(priv, reg, RXCHK_CONTROL);
  2231. }
  2232. /* Flush RX pipe */
  2233. if (!priv->wolopts)
  2234. topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
  2235. ret = tdma_enable_set(priv, 0);
  2236. if (ret) {
  2237. netdev_err(dev, "TDMA timeout!\n");
  2238. return ret;
  2239. }
  2240. /* Wait for a packet boundary */
  2241. usleep_range(2000, 3000);
  2242. umac_enable_set(priv, CMD_TX_EN, 0);
  2243. topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
  2244. /* Free RX/TX rings SW structures */
  2245. for (i = 0; i < dev->num_tx_queues; i++)
  2246. bcm_sysport_fini_tx_ring(priv, i);
  2247. bcm_sysport_fini_rx_ring(priv);
  2248. /* Get prepared for Wake-on-LAN */
  2249. if (device_may_wakeup(d) && priv->wolopts)
  2250. ret = bcm_sysport_suspend_to_wol(priv);
  2251. return ret;
  2252. }
  2253. static int __maybe_unused bcm_sysport_resume(struct device *d)
  2254. {
  2255. struct net_device *dev = dev_get_drvdata(d);
  2256. struct bcm_sysport_priv *priv = netdev_priv(dev);
  2257. unsigned int i;
  2258. u32 reg;
  2259. int ret;
  2260. if (!netif_running(dev))
  2261. return 0;
  2262. umac_reset(priv);
  2263. /* Disable the UniMAC RX/TX */
  2264. umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
  2265. /* We may have been suspended and never received a WOL event that
  2266. * would turn off MPD detection, take care of that now
  2267. */
  2268. bcm_sysport_resume_from_wol(priv);
  2269. /* Initialize both hardware and software ring */
  2270. for (i = 0; i < dev->num_tx_queues; i++) {
  2271. ret = bcm_sysport_init_tx_ring(priv, i);
  2272. if (ret) {
  2273. netdev_err(dev, "failed to initialize TX ring %d\n",
  2274. i);
  2275. goto out_free_tx_rings;
  2276. }
  2277. }
  2278. /* Initialize linked-list */
  2279. tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
  2280. /* Initialize RX ring */
  2281. ret = bcm_sysport_init_rx_ring(priv);
  2282. if (ret) {
  2283. netdev_err(dev, "failed to initialize RX ring\n");
  2284. goto out_free_rx_ring;
  2285. }
  2286. /* RX pipe enable */
  2287. topctrl_writel(priv, 0, RX_FLUSH_CNTL);
  2288. ret = rdma_enable_set(priv, 1);
  2289. if (ret) {
  2290. netdev_err(dev, "failed to enable RDMA\n");
  2291. goto out_free_rx_ring;
  2292. }
  2293. /* Enable rxhck */
  2294. if (priv->rx_chk_en) {
  2295. reg = rxchk_readl(priv, RXCHK_CONTROL);
  2296. reg |= RXCHK_EN;
  2297. rxchk_writel(priv, reg, RXCHK_CONTROL);
  2298. }
  2299. rbuf_init(priv);
  2300. /* Set maximum frame length */
  2301. if (!priv->is_lite)
  2302. umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
  2303. else
  2304. gib_set_pad_extension(priv);
  2305. /* Set MAC address */
  2306. umac_set_hw_addr(priv, dev->dev_addr);
  2307. umac_enable_set(priv, CMD_RX_EN, 1);
  2308. /* TX pipe enable */
  2309. topctrl_writel(priv, 0, TX_FLUSH_CNTL);
  2310. umac_enable_set(priv, CMD_TX_EN, 1);
  2311. ret = tdma_enable_set(priv, 1);
  2312. if (ret) {
  2313. netdev_err(dev, "TDMA timeout!\n");
  2314. goto out_free_rx_ring;
  2315. }
  2316. phy_resume(dev->phydev);
  2317. bcm_sysport_netif_start(dev);
  2318. netif_device_attach(dev);
  2319. return 0;
  2320. out_free_rx_ring:
  2321. bcm_sysport_fini_rx_ring(priv);
  2322. out_free_tx_rings:
  2323. for (i = 0; i < dev->num_tx_queues; i++)
  2324. bcm_sysport_fini_tx_ring(priv, i);
  2325. return ret;
  2326. }
  2327. static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
  2328. bcm_sysport_suspend, bcm_sysport_resume);
  2329. static struct platform_driver bcm_sysport_driver = {
  2330. .probe = bcm_sysport_probe,
  2331. .remove = bcm_sysport_remove,
  2332. .driver = {
  2333. .name = "brcm-systemport",
  2334. .of_match_table = bcm_sysport_of_match,
  2335. .pm = &bcm_sysport_pm_ops,
  2336. },
  2337. };
  2338. module_platform_driver(bcm_sysport_driver);
  2339. MODULE_AUTHOR("Broadcom Corporation");
  2340. MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
  2341. MODULE_ALIAS("platform:brcm-systemport");
  2342. MODULE_LICENSE("GPL");