mach-at2440evb.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
  4. // Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
  5. // and modifications by SBZ <sbz@spgui.org> and
  6. // Weibing <http://weibing.blogbus.com>
  7. //
  8. // For product information, visit http://www.arm.com/
  9. #include <linux/kernel.h>
  10. #include <linux/types.h>
  11. #include <linux/gpio.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/list.h>
  14. #include <linux/timer.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/serial_s3c.h>
  19. #include <linux/dm9000.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/map.h>
  23. #include <asm/mach/irq.h>
  24. #include <mach/hardware.h>
  25. #include <mach/fb.h>
  26. #include <asm/irq.h>
  27. #include <asm/mach-types.h>
  28. #include <mach/regs-gpio.h>
  29. #include <mach/regs-lcd.h>
  30. #include <mach/gpio-samsung.h>
  31. #include <linux/platform_data/mtd-nand-s3c2410.h>
  32. #include <linux/platform_data/i2c-s3c2410.h>
  33. #include <linux/mtd/mtd.h>
  34. #include <linux/mtd/rawnand.h>
  35. #include <linux/mtd/nand_ecc.h>
  36. #include <linux/mtd/partitions.h>
  37. #include <plat/devs.h>
  38. #include <plat/cpu.h>
  39. #include <linux/platform_data/mmc-s3cmci.h>
  40. #include <plat/samsung-time.h>
  41. #include "common.h"
  42. static struct map_desc at2440evb_iodesc[] __initdata = {
  43. /* Nothing here */
  44. };
  45. #define UCON S3C2410_UCON_DEFAULT
  46. #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
  47. #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
  48. static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
  49. [0] = {
  50. .hwport = 0,
  51. .flags = 0,
  52. .ucon = UCON,
  53. .ulcon = ULCON,
  54. .ufcon = UFCON,
  55. .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
  56. },
  57. [1] = {
  58. .hwport = 1,
  59. .flags = 0,
  60. .ucon = UCON,
  61. .ulcon = ULCON,
  62. .ufcon = UFCON,
  63. .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
  64. },
  65. };
  66. /* NAND Flash on AT2440EVB board */
  67. static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
  68. [0] = {
  69. .name = "Boot Agent",
  70. .size = SZ_256K,
  71. .offset = 0,
  72. },
  73. [1] = {
  74. .name = "Kernel",
  75. .size = SZ_2M,
  76. .offset = SZ_256K,
  77. },
  78. [2] = {
  79. .name = "Root",
  80. .offset = SZ_256K + SZ_2M,
  81. .size = MTDPART_SIZ_FULL,
  82. },
  83. };
  84. static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
  85. [0] = {
  86. .name = "nand",
  87. .nr_chips = 1,
  88. .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
  89. .partitions = at2440evb_default_nand_part,
  90. },
  91. };
  92. static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
  93. .tacls = 25,
  94. .twrph0 = 55,
  95. .twrph1 = 40,
  96. .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
  97. .sets = at2440evb_nand_sets,
  98. .ecc_mode = NAND_ECC_SOFT,
  99. };
  100. /* DM9000AEP 10/100 ethernet controller */
  101. static struct resource at2440evb_dm9k_resource[] = {
  102. [0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
  103. [1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
  104. [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
  105. | IORESOURCE_IRQ_HIGHEDGE),
  106. };
  107. static struct dm9000_plat_data at2440evb_dm9k_pdata = {
  108. .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
  109. };
  110. static struct platform_device at2440evb_device_eth = {
  111. .name = "dm9000",
  112. .id = -1,
  113. .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
  114. .resource = at2440evb_dm9k_resource,
  115. .dev = {
  116. .platform_data = &at2440evb_dm9k_pdata,
  117. },
  118. };
  119. static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
  120. .gpio_detect = S3C2410_GPG(10),
  121. };
  122. /* 7" LCD panel */
  123. static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
  124. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  125. S3C2410_LCDCON5_INVVLINE |
  126. S3C2410_LCDCON5_INVVFRAME |
  127. S3C2410_LCDCON5_PWREN |
  128. S3C2410_LCDCON5_HWSWP,
  129. .type = S3C2410_LCDCON1_TFT,
  130. .width = 800,
  131. .height = 480,
  132. .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
  133. .xres = 800,
  134. .yres = 480,
  135. .bpp = 16,
  136. .left_margin = 88,
  137. .right_margin = 40,
  138. .hsync_len = 128,
  139. .upper_margin = 32,
  140. .lower_margin = 11,
  141. .vsync_len = 2,
  142. };
  143. static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
  144. .displays = &at2440evb_lcd_cfg,
  145. .num_displays = 1,
  146. .default_display = 0,
  147. };
  148. static struct platform_device *at2440evb_devices[] __initdata = {
  149. &s3c_device_ohci,
  150. &s3c_device_wdt,
  151. &s3c_device_adc,
  152. &s3c_device_i2c0,
  153. &s3c_device_rtc,
  154. &s3c_device_nand,
  155. &s3c_device_sdi,
  156. &s3c_device_lcd,
  157. &at2440evb_device_eth,
  158. };
  159. static void __init at2440evb_map_io(void)
  160. {
  161. s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
  162. s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
  163. samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
  164. }
  165. static void __init at2440evb_init_time(void)
  166. {
  167. s3c2440_init_clocks(16934400);
  168. samsung_timer_init();
  169. }
  170. static void __init at2440evb_init(void)
  171. {
  172. s3c24xx_fb_set_platdata(&at2440evb_fb_info);
  173. s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
  174. s3c_nand_set_platdata(&at2440evb_nand_info);
  175. s3c_i2c0_set_platdata(NULL);
  176. platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
  177. }
  178. MACHINE_START(AT2440EVB, "AT2440EVB")
  179. .atag_offset = 0x100,
  180. .map_io = at2440evb_map_io,
  181. .init_machine = at2440evb_init,
  182. .init_irq = s3c2440_init_irq,
  183. .init_time = at2440evb_init_time,
  184. MACHINE_END