gcw0.dts 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include "jz4770.dtsi"
  4. / {
  5. compatible = "gcw,zero", "ingenic,jz4770";
  6. model = "GCW Zero";
  7. aliases {
  8. serial0 = &uart0;
  9. serial1 = &uart1;
  10. serial2 = &uart2;
  11. serial3 = &uart3;
  12. };
  13. chosen {
  14. stdout-path = "serial2:57600n8";
  15. };
  16. board {
  17. compatible = "simple-bus";
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. ranges;
  21. otg_phy: otg-phy {
  22. compatible = "usb-nop-xceiv";
  23. clocks = <&cgu JZ4770_CLK_OTG_PHY>;
  24. clock-names = "main_clk";
  25. };
  26. };
  27. };
  28. &ext {
  29. clock-frequency = <12000000>;
  30. };
  31. &uart2 {
  32. status = "okay";
  33. };
  34. &cgu {
  35. /* Put high-speed peripherals under PLL1, such that we can change the
  36. * PLL0 frequency on demand without having to suspend peripherals.
  37. * We use a rate of 432 MHz, which is the least common multiple of
  38. * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
  39. */
  40. assigned-clocks =
  41. <&cgu JZ4770_CLK_PLL1>,
  42. <&cgu JZ4770_CLK_UHC>;
  43. assigned-clock-parents =
  44. <0>,
  45. <&cgu JZ4770_CLK_PLL1>;
  46. assigned-clock-rates =
  47. <432000000>;
  48. };
  49. &uhc {
  50. /* The WiFi module is connected to the UHC. */
  51. status = "okay";
  52. };