首頁 探索 說明
註冊 登入
RD_Software
/
linux-arkmicro
2
0
複刻 1
Files 問題管理 0 合併請求 0 Wiki
分支: master
分支列表 標籤列表
linux-arkmicro
/
linux
/
arch
/
s390
/
kernel
/
perf_cpum_cf_events.c

perf_cpum_cf_events.c 27 KB
永久連結 文件歷史 原始文件

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598 
  1. // SPDX-License-Identifier: GPL-2.0
    2. 

  2. /*
    3. 

  3.  * Perf PMU sysfs events attributes for available CPU-measurement counters
    4. 

  4.  *
    5. 

  5.  */
    6. 

  6. 

  7. #include <linux/slab.h>
    8. 

  8. #include <linux/perf_event.h>
    9. 

  9. 

  10. 

  11. /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
    12. 

  12. 

  13. CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
    14. 

  14. CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
    15. 

  15. CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
    16. 

  16. CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
    17. 

  17. CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
    18. 

  18. CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
    19. 

  19. CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
    20. 

  20. CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
    21. 

  21. CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
    22. 

  22. CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
    23. 

  23. CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
    24. 

  24. CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
    25. 

  25. CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
    26. 

  26. CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
    27. 

  27. CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
    28. 

  28. CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
    29. 

  29. CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
    30. 

  30. CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
    31. 

  31. CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
    32. 

  32. CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
    33. 

  33. CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_FUNCTIONS, 0x0040);
    34. 

  34. CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_CYCLES, 0x0041);
    35. 

  35. CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS, 0x0042);
    36. 

  36. CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_CYCLES, 0x0043);
    37. 

  37. CPUMF_EVENT_ATTR(cf_svn_generic, SHA_FUNCTIONS, 0x0044);
    38. 

  38. CPUMF_EVENT_ATTR(cf_svn_generic, SHA_CYCLES, 0x0045);
    39. 

  39. CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS, 0x0046);
    40. 

  40. CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_CYCLES, 0x0047);
    41. 

  41. CPUMF_EVENT_ATTR(cf_svn_generic, DEA_FUNCTIONS, 0x0048);
    42. 

  42. CPUMF_EVENT_ATTR(cf_svn_generic, DEA_CYCLES, 0x0049);
    43. 

  43. CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS, 0x004a);
    44. 

  44. CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_CYCLES, 0x004b);
    45. 

  45. CPUMF_EVENT_ATTR(cf_svn_generic, AES_FUNCTIONS, 0x004c);
    46. 

  46. CPUMF_EVENT_ATTR(cf_svn_generic, AES_CYCLES, 0x004d);
    47. 

  47. CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS, 0x004e);
    48. 

  48. CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_CYCLES, 0x004f);
    49. 

  49. CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
    50. 

  50. CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
    51. 

  51. CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
    52. 

  52. CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
    53. 

  53. CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
    54. 

  54. CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
    55. 

  55. CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
    56. 

  56. CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
    57. 

  57. CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
    58. 

  58. CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
    59. 

  59. CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
    60. 

  60. CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
    61. 

  61. CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
    62. 

  62. CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
    63. 

  63. CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
    64. 

  64. CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
    65. 

  65. CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
    66. 

  66. CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
    67. 

  67. CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
    68. 

  68. CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
    69. 

  69. CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
    70. 

  70. CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
    71. 

  71. CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
    72. 

  72. CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
    73. 

  73. CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
    74. 

  74. CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
    75. 

  75. CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
    76. 

  76. CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
    77. 

  77. CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
    78. 

  78. CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
    79. 

  79. CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
    80. 

  80. CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
    81. 

  81. CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
    82. 

  82. CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
    83. 

  83. CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
    84. 

  84. CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
    85. 

  85. CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
    86. 

  86. CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
    87. 

  87. CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
    88. 

  88. CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
    89. 

  89. CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
    90. 

  90. CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
    91. 

  91. CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
    92. 

  92. CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
    93. 

  93. CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
    94. 

  94. CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
    95. 

  95. CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
    96. 

  96. CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
    97. 

  97. CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
    98. 

  98. CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
    99. 

  99. CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
    100. 

  100. CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
    101. 

  101. CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
    102. 

  102. CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
    103. 

  103. CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
    104. 

  104. CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
    105. 

  105. CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
    106. 

  106. CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
    107. 

  107. CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
    108. 

  108. CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
    109. 

  109. CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
    110. 

  110. CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
    111. 

  111. CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
    112. 

  112. CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
    113. 

  113. CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
    114. 

  114. CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
    115. 

  115. CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
    116. 

  116. CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
    117. 

  117. CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
    118. 

  118. CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
    119. 

  119. CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
    120. 

  120. CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
    121. 

  121. CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
    122. 

  122. CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
    123. 

  123. CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
    124. 

  124. CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
    125. 

  125. CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
    126. 

  126. CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
    127. 

  127. CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
    128. 

  128. CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
    129. 

  129. CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
    130. 

  130. CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
    131. 

  131. CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
    132. 

  132. CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
    133. 

  133. CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
    134. 

  134. CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
    135. 

  135. CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
    136. 

  136. CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
    137. 

  137. CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
    138. 

  138. CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
    139. 

  139. CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
    140. 

  140. CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
    141. 

  141. CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
    142. 

  142. CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
    143. 

  143. CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
    144. 

  144. CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
    145. 

  145. CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
    146. 

  146. CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
    147. 

  147. CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
    148. 

  148. CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
    149. 

  149. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
    150. 

  150. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
    151. 

  151. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
    152. 

  152. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
    153. 

  153. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
    154. 

  154. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
    155. 

  155. CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
    156. 

  156. CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
    157. 

  157. CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
    158. 

  158. CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
    159. 

  159. CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
    160. 

  160. CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
    161. 

  161. CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
    162. 

  162. CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
    163. 

  163. CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
    164. 

  164. CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
    165. 

  165. CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
    166. 

  166. CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
    167. 

  167. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
    168. 

  168. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
    169. 

  169. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
    170. 

  170. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
    171. 

  171. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
    172. 

  172. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
    173. 

  173. CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
    174. 

  174. CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
    175. 

  175. CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
    176. 

  176. CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
    177. 

  177. CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
    178. 

  178. CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
    179. 

  179. CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
    180. 

  180. CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
    181. 

  181. CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
    182. 

  182. CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
    183. 

  183. CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
    184. 

  184. CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
    185. 

  185. CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
    186. 

  186. CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
    187. 

  187. CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
    188. 

  188. CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
    189. 

  189. CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
    190. 

  190. CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
    191. 

  191. CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
    192. 

  192. CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
    193. 

  193. CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
    194. 

  194. CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
    195. 

  195. CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
    196. 

  196. CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
    197. 

  197. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
    198. 

  198. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
    199. 

  199. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
    200. 

  200. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
    201. 

  201. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
    202. 

  202. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
    203. 

  203. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
    204. 

  204. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
    205. 

  205. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
    206. 

  206. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
    207. 

  207. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
    208. 

  208. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
    209. 

  209. CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
    210. 

  210. CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
    211. 

  211. CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
    212. 

  212. CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
    213. 

  213. CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
    214. 

  214. CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
    215. 

  215. CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
    216. 

  216. CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
    217. 

  217. CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
    218. 

  218. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
    219. 

  219. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
    220. 

  220. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
    221. 

  221. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
    222. 

  222. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
    223. 

  223. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
    224. 

  224. CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
    225. 

  225. CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
    226. 

  226. CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
    227. 

  227. CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
    228. 

  228. CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
    229. 

  229. CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
    230. 

  230. CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
    231. 

  231. CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
    232. 

  232. CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
    233. 

  233. CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
    234. 

  234. CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
    235. 

  235. 

  236. static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
    237. 

  237. 	CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
    238. 

  238. 	CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
    239. 

  239. 	CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
    240. 

  240. 	CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
    241. 

  241. 	CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
    242. 

  242. 	CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
    243. 

  243. 	CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
    244. 

  244. 	CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
    245. 

  245. 	CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
    246. 

  246. 	CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
    247. 

  247. 	CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
    248. 

  248. 	CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
    249. 

  249. 	NULL,
    250. 

  250. };
    251. 

  251. 

  252. static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
    253. 

  253. 	CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
    254. 

  254. 	CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
    255. 

  255. 	CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
    256. 

  256. 	CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
    257. 

  257. 	CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
    258. 

  258. 	CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
    259. 

  259. 	CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
    260. 

  260. 	CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
    261. 

  261. 	NULL,
    262. 

  262. };
    263. 

  263. 

  264. static struct attribute *cpumcf_svn_generic_pmu_event_attr[] __initdata = {
    265. 

  265. 	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_FUNCTIONS),
    266. 

  266. 	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_CYCLES),
    267. 

  267. 	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS),
    268. 

  268. 	CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_CYCLES),
    269. 

  269. 	CPUMF_EVENT_PTR(cf_svn_generic, SHA_FUNCTIONS),
    270. 

  270. 	CPUMF_EVENT_PTR(cf_svn_generic, SHA_CYCLES),
    271. 

  271. 	CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS),
    272. 

  272. 	CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_CYCLES),
    273. 

  273. 	CPUMF_EVENT_PTR(cf_svn_generic, DEA_FUNCTIONS),
    274. 

  274. 	CPUMF_EVENT_PTR(cf_svn_generic, DEA_CYCLES),
    275. 

  275. 	CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS),
    276. 

  276. 	CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_CYCLES),
    277. 

  277. 	CPUMF_EVENT_PTR(cf_svn_generic, AES_FUNCTIONS),
    278. 

  278. 	CPUMF_EVENT_PTR(cf_svn_generic, AES_CYCLES),
    279. 

  279. 	CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS),
    280. 

  280. 	CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_CYCLES),
    281. 

  281. 	NULL,
    282. 

  282. };
    283. 

  283. 

  284. static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
    285. 

  285. 	CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
    286. 

  286. 	CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
    287. 

  287. 	CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
    288. 

  288. 	CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
    289. 

  289. 	CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
    290. 

  290. 	CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
    291. 

  291. 	CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
    292. 

  292. 	CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
    293. 

  293. 	CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
    294. 

  294. 	CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
    295. 

  295. 	CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
    296. 

  296. 	CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
    297. 

  297. 	CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
    298. 

  298. 	CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
    299. 

  299. 	CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
    300. 

  300. 	CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
    301. 

  301. 	CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
    302. 

  302. 	CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
    303. 

  303. 	NULL,
    304. 

  304. };
    305. 

  305. 

  306. static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
    307. 

  307. 	CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
    308. 

  308. 	CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
    309. 

  309. 	CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
    310. 

  310. 	CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
    311. 

  311. 	CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
    312. 

  312. 	CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
    313. 

  313. 	CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
    314. 

  314. 	CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
    315. 

  315. 	CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
    316. 

  316. 	CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
    317. 

  317. 	CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
    318. 

  318. 	CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
    319. 

  319. 	CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
    320. 

  320. 	CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
    321. 

  321. 	CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
    322. 

  322. 	CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
    323. 

  323. 	CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
    324. 

  324. 	CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
    325. 

  325. 	CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
    326. 

  326. 	CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
    327. 

  327. 	CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
    328. 

  328. 	CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
    329. 

  329. 	CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
    330. 

  330. 	CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
    331. 

  331. 	NULL,
    332. 

  332. };
    333. 

  333. 

  334. static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
    335. 

  335. 	CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
    336. 

  336. 	CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
    337. 

  337. 	CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
    338. 

  338. 	CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
    339. 

  339. 	CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
    340. 

  340. 	CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
    341. 

  341. 	CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
    342. 

  342. 	CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
    343. 

  343. 	CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
    344. 

  344. 	CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
    345. 

  345. 	CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
    346. 

  346. 	CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
    347. 

  347. 	CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
    348. 

  348. 	CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
    349. 

  349. 	CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
    350. 

  350. 	CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
    351. 

  351. 	CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
    352. 

  352. 	CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
    353. 

  353. 	CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
    354. 

  354. 	CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
    355. 

  355. 	CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
    356. 

  356. 	CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
    357. 

  357. 	CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
    358. 

  358. 	CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
    359. 

  359. 	CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
    360. 

  360. 	CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
    361. 

  361. 	CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
    362. 

  362. 	CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
    363. 

  363. 	CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
    364. 

  364. 	CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
    365. 

  365. 	CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
    366. 

  366. 	CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
    367. 

  367. 	CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
    368. 

  368. 	CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
    369. 

  369. 	CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
    370. 

  370. 	NULL,
    371. 

  371. };
    372. 

  372. 

  373. static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
    374. 

  374. 	CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
    375. 

  375. 	CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
    376. 

  376. 	CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
    377. 

  377. 	CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
    378. 

  378. 	CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
    379. 

  379. 	CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
    380. 

  380. 	CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
    381. 

  381. 	CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
    382. 

  382. 	CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
    383. 

  383. 	CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
    384. 

  384. 	CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
    385. 

  385. 	CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
    386. 

  386. 	CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
    387. 

  387. 	CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
    388. 

  388. 	CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
    389. 

  389. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
    390. 

  390. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
    391. 

  391. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
    392. 

  392. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
    393. 

  393. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
    394. 

  394. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
    395. 

  395. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
    396. 

  396. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
    397. 

  397. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
    398. 

  398. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
    399. 

  399. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
    400. 

  400. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
    401. 

  401. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
    402. 

  402. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
    403. 

  403. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
    404. 

  404. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
    405. 

  405. 	CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
    406. 

  406. 	CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
    407. 

  407. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
    408. 

  408. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
    409. 

  409. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
    410. 

  410. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
    411. 

  411. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
    412. 

  412. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
    413. 

  413. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
    414. 

  414. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
    415. 

  415. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
    416. 

  416. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
    417. 

  417. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
    418. 

  418. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
    419. 

  419. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
    420. 

  420. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
    421. 

  421. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
    422. 

  422. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
    423. 

  423. 	CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
    424. 

  424. 	CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
    425. 

  425. 	CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
    426. 

  426. 	CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
    427. 

  427. 	CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
    428. 

  428. 	CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
    429. 

  429. 	CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
    430. 

  430. 	NULL,
    431. 

  431. };
    432. 

  432. 

  433. static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
    434. 

  434. 	CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
    435. 

  435. 	CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
    436. 

  436. 	CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
    437. 

  437. 	CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
    438. 

  438. 	CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
    439. 

  439. 	CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
    440. 

  440. 	CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
    441. 

  441. 	CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
    442. 

  442. 	CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
    443. 

  443. 	CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
    444. 

  444. 	CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
    445. 

  445. 	CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
    446. 

  446. 	CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
    447. 

  447. 	CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
    448. 

  448. 	CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
    449. 

  449. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
    450. 

  450. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
    451. 

  451. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
    452. 

  452. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
    453. 

  453. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
    454. 

  454. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
    455. 

  455. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
    456. 

  456. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
    457. 

  457. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
    458. 

  458. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
    459. 

  459. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
    460. 

  460. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
    461. 

  461. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
    462. 

  462. 	CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
    463. 

  463. 	CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
    464. 

  464. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
    465. 

  465. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
    466. 

  466. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
    467. 

  467. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
    468. 

  468. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
    469. 

  469. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
    470. 

  470. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
    471. 

  471. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
    472. 

  472. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
    473. 

  473. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
    474. 

  474. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
    475. 

  475. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
    476. 

  476. 	CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
    477. 

  477. 	CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
    478. 

  478. 	CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
    479. 

  479. 	CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
    480. 

  480. 	CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
    481. 

  481. 	CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
    482. 

  482. 	CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
    483. 

  483. 	CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
    484. 

  484. 	CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
    485. 

  485. 	CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
    486. 

  486. 	CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
    487. 

  487. 	NULL,
    488. 

  488. };
    489. 

  489. 

  490. /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
    491. 

  491. 

  492. static struct attribute_group cpumcf_pmu_events_group = {
    493. 

  493. 	.name = "events",
    494. 

  494. };
    495. 

  495. 

  496. PMU_FORMAT_ATTR(event, "config:0-63");
    497. 

  497. 

  498. static struct attribute *cpumcf_pmu_format_attr[] = {
    499. 

  499. 	&format_attr_event.attr,
    500. 

  500. 	NULL,
    501. 

  501. };
    502. 

  502. 

  503. static struct attribute_group cpumcf_pmu_format_group = {
    504. 

  504. 	.name = "format",
    505. 

  505. 	.attrs = cpumcf_pmu_format_attr,
    506. 

  506. };
    507. 

  507. 

  508. static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
    509. 

  509. 	&cpumcf_pmu_events_group,
    510. 

  510. 	&cpumcf_pmu_format_group,
    511. 

  511. 	NULL,
    512. 

  512. };
    513. 

  513. 

  514. 

  515. static __init struct attribute **merge_attr(struct attribute **a,
    516. 

  516. 					    struct attribute **b,
    517. 

  517. 					    struct attribute **c)
    518. 

  518. {
    519. 

  519. 	struct attribute **new;
    520. 

  520. 	int j, i;
    521. 

  521. 

  522. 	for (j = 0; a[j]; j++)
    523. 

  523. 		;
    524. 

  524. 	for (i = 0; b[i]; i++)
    525. 

  525. 		j++;
    526. 

  526. 	for (i = 0; c[i]; i++)
    527. 

  527. 		j++;
    528. 

  528. 	j++;
    529. 

  529. 

  530. 	new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
    531. 

  531. 	if (!new)
    532. 

  532. 		return NULL;
    533. 

  533. 	j = 0;
    534. 

  534. 	for (i = 0; a[i]; i++)
    535. 

  535. 		new[j++] = a[i];
    536. 

  536. 	for (i = 0; b[i]; i++)
    537. 

  537. 		new[j++] = b[i];
    538. 

  538. 	for (i = 0; c[i]; i++)
    539. 

  539. 		new[j++] = c[i];
    540. 

  540. 	new[j] = NULL;
    541. 

  541. 

  542. 	return new;
    543. 

  543. }
    544. 

  544. 

  545. __init const struct attribute_group **cpumf_cf_event_group(void)
    546. 

  546. {
    547. 

  547. 	struct attribute **combined, **model, **cfvn, **csvn;
    548. 

  548. 	struct attribute *none[] = { NULL };
    549. 

  549. 	struct cpumf_ctr_info ci;
    550. 

  550. 	struct cpuid cpu_id;
    551. 

  551. 

  552. 	/* Determine generic counters set(s) */
    553. 

  553. 	qctri(&ci);
    554. 

  554. 	switch (ci.cfvn) {
    555. 

  555. 	case 1:
    556. 

  556. 		cfvn = cpumcf_fvn1_pmu_event_attr;
    557. 

  557. 		break;
    558. 

  558. 	case 3:
    559. 

  559. 		cfvn = cpumcf_fvn3_pmu_event_attr;
    560. 

  560. 		break;
    561. 

  561. 	default:
    562. 

  562. 		cfvn = none;
    563. 

  563. 	}
    564. 

  564. 	csvn = cpumcf_svn_generic_pmu_event_attr;
    565. 

  565. 

  566. 	/* Determine model-specific counter set(s) */
    567. 

  567. 	get_cpu_id(&cpu_id);
    568. 

  568. 	switch (cpu_id.machine) {
    569. 

  569. 	case 0x2097:
    570. 

  570. 	case 0x2098:
    571. 

  571. 		model = cpumcf_z10_pmu_event_attr;
    572. 

  572. 		break;
    573. 

  573. 	case 0x2817:
    574. 

  574. 	case 0x2818:
    575. 

  575. 		model = cpumcf_z196_pmu_event_attr;
    576. 

  576. 		break;
    577. 

  577. 	case 0x2827:
    578. 

  578. 	case 0x2828:
    579. 

  579. 		model = cpumcf_zec12_pmu_event_attr;
    580. 

  580. 		break;
    581. 

  581. 	case 0x2964:
    582. 

  582. 	case 0x2965:
    583. 

  583. 		model = cpumcf_z13_pmu_event_attr;
    584. 

  584. 		break;
    585. 

  585. 	case 0x3906:
    586. 

  586. 	case 0x3907:
    587. 

  587. 		model = cpumcf_z14_pmu_event_attr;
    588. 

  588. 		break;
    589. 

  589. 	default:
    590. 

  590. 		model = none;
    591. 

  591. 		break;
    592. 

  592. 	}
    593. 

  593. 

  594. 	combined = merge_attr(cfvn, csvn, model);
    595. 

  595. 	if (combined)
    596. 

  596. 		cpumcf_pmu_events_group.attrs = combined;
    597. 

  597. 	return cpumcf_pmu_attr_groups;
    598. 

  598. }
    599.