clk-mt2701-hif.c 2.2 KB

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  1. /*
  2. * Copyright (c) 2014 MediaTek Inc.
  3. * Author: Shunli Wang <shunli.wang@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/clk-provider.h>
  15. #include <linux/platform_device.h>
  16. #include "clk-mtk.h"
  17. #include "clk-gate.h"
  18. #include <dt-bindings/clock/mt2701-clk.h>
  19. static const struct mtk_gate_regs hif_cg_regs = {
  20. .sta_ofs = 0x0030,
  21. };
  22. #define GATE_HIF(_id, _name, _parent, _shift) { \
  23. .id = _id, \
  24. .name = _name, \
  25. .parent_name = _parent, \
  26. .regs = &hif_cg_regs, \
  27. .shift = _shift, \
  28. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  29. }
  30. static const struct mtk_gate hif_clks[] = {
  31. GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
  32. GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
  33. GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
  34. GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
  35. GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
  36. };
  37. static const struct of_device_id of_match_clk_mt2701_hif[] = {
  38. { .compatible = "mediatek,mt2701-hifsys", },
  39. {}
  40. };
  41. static int clk_mt2701_hif_probe(struct platform_device *pdev)
  42. {
  43. struct clk_onecell_data *clk_data;
  44. int r;
  45. struct device_node *node = pdev->dev.of_node;
  46. clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
  47. mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
  48. clk_data);
  49. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  50. if (r) {
  51. dev_err(&pdev->dev,
  52. "could not register clock provider: %s: %d\n",
  53. pdev->name, r);
  54. return r;
  55. }
  56. mtk_register_reset_controller(node, 1, 0x34);
  57. return 0;
  58. }
  59. static struct platform_driver clk_mt2701_hif_drv = {
  60. .probe = clk_mt2701_hif_probe,
  61. .driver = {
  62. .name = "clk-mt2701-hif",
  63. .of_match_table = of_match_clk_mt2701_hif,
  64. },
  65. };
  66. builtin_platform_driver(clk_mt2701_hif_drv);