ccu-sun9i-a80-usb.c 4.3 KB

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  1. /*
  2. * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/of_address.h>
  16. #include <linux/platform_device.h>
  17. #include "ccu_common.h"
  18. #include "ccu_gate.h"
  19. #include "ccu_reset.h"
  20. #include "ccu-sun9i-a80-usb.h"
  21. static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0);
  22. static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0);
  23. static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0);
  24. static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0);
  25. static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0);
  26. static SUNXI_CCU_GATE(usb0_phy_clk, "usb0-phy", "osc24M", 0x4, BIT(1), 0);
  27. static SUNXI_CCU_GATE(usb1_hsic_clk, "usb1-hsic", "osc24M", 0x4, BIT(2), 0);
  28. static SUNXI_CCU_GATE(usb1_phy_clk, "usb1-phy", "osc24M", 0x4, BIT(3), 0);
  29. static SUNXI_CCU_GATE(usb2_hsic_clk, "usb2-hsic", "osc24M", 0x4, BIT(4), 0);
  30. static SUNXI_CCU_GATE(usb2_phy_clk, "usb2-phy", "osc24M", 0x4, BIT(5), 0);
  31. static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "osc24M", 0x4, BIT(10), 0);
  32. static struct ccu_common *sun9i_a80_usb_clks[] = {
  33. &bus_hci0_clk.common,
  34. &usb_ohci0_clk.common,
  35. &bus_hci1_clk.common,
  36. &bus_hci2_clk.common,
  37. &usb_ohci2_clk.common,
  38. &usb0_phy_clk.common,
  39. &usb1_hsic_clk.common,
  40. &usb1_phy_clk.common,
  41. &usb2_hsic_clk.common,
  42. &usb2_phy_clk.common,
  43. &usb_hsic_clk.common,
  44. };
  45. static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
  46. .hws = {
  47. [CLK_BUS_HCI0] = &bus_hci0_clk.common.hw,
  48. [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
  49. [CLK_BUS_HCI1] = &bus_hci1_clk.common.hw,
  50. [CLK_BUS_HCI2] = &bus_hci2_clk.common.hw,
  51. [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
  52. [CLK_USB0_PHY] = &usb0_phy_clk.common.hw,
  53. [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw,
  54. [CLK_USB1_PHY] = &usb1_phy_clk.common.hw,
  55. [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw,
  56. [CLK_USB2_PHY] = &usb2_phy_clk.common.hw,
  57. [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
  58. },
  59. .num = CLK_NUMBER,
  60. };
  61. static struct ccu_reset_map sun9i_a80_usb_resets[] = {
  62. [RST_USB0_HCI] = { 0x0, BIT(17) },
  63. [RST_USB1_HCI] = { 0x0, BIT(18) },
  64. [RST_USB2_HCI] = { 0x0, BIT(19) },
  65. [RST_USB0_PHY] = { 0x4, BIT(17) },
  66. [RST_USB1_HSIC] = { 0x4, BIT(18) },
  67. [RST_USB1_PHY] = { 0x4, BIT(19) },
  68. [RST_USB2_HSIC] = { 0x4, BIT(20) },
  69. [RST_USB2_PHY] = { 0x4, BIT(21) },
  70. };
  71. static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = {
  72. .ccu_clks = sun9i_a80_usb_clks,
  73. .num_ccu_clks = ARRAY_SIZE(sun9i_a80_usb_clks),
  74. .hw_clks = &sun9i_a80_usb_hw_clks,
  75. .resets = sun9i_a80_usb_resets,
  76. .num_resets = ARRAY_SIZE(sun9i_a80_usb_resets),
  77. };
  78. static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
  79. {
  80. struct resource *res;
  81. struct clk *bus_clk;
  82. void __iomem *reg;
  83. int ret;
  84. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  85. reg = devm_ioremap_resource(&pdev->dev, res);
  86. if (IS_ERR(reg))
  87. return PTR_ERR(reg);
  88. bus_clk = devm_clk_get(&pdev->dev, "bus");
  89. if (IS_ERR(bus_clk)) {
  90. ret = PTR_ERR(bus_clk);
  91. if (ret != -EPROBE_DEFER)
  92. dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
  93. return ret;
  94. }
  95. /* The bus clock needs to be enabled for us to access the registers */
  96. ret = clk_prepare_enable(bus_clk);
  97. if (ret) {
  98. dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
  99. return ret;
  100. }
  101. ret = sunxi_ccu_probe(pdev->dev.of_node, reg,
  102. &sun9i_a80_usb_clk_desc);
  103. if (ret)
  104. goto err_disable_clk;
  105. return 0;
  106. err_disable_clk:
  107. clk_disable_unprepare(bus_clk);
  108. return ret;
  109. }
  110. static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
  111. { .compatible = "allwinner,sun9i-a80-usb-clks" },
  112. { }
  113. };
  114. static struct platform_driver sun9i_a80_usb_clk_driver = {
  115. .probe = sun9i_a80_usb_clk_probe,
  116. .driver = {
  117. .name = "sun9i-a80-usb-clks",
  118. .of_match_table = sun9i_a80_usb_clk_ids,
  119. },
  120. };
  121. builtin_platform_driver(sun9i_a80_usb_clk_driver);