ib_verbs.c 102 KB

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  1. /*
  2. * Broadcom NetXtreme-E RoCE driver.
  3. *
  4. * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
  5. * Broadcom refers to Broadcom Limited and/or its subsidiaries.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or without
  14. * modification, are permitted provided that the following conditions
  15. * are met:
  16. *
  17. * 1. Redistributions of source code must retain the above copyright
  18. * notice, this list of conditions and the following disclaimer.
  19. * 2. Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the
  22. * distribution.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33. * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34. * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. *
  36. * Description: IB Verbs interpreter
  37. */
  38. #include <linux/interrupt.h>
  39. #include <linux/types.h>
  40. #include <linux/pci.h>
  41. #include <linux/netdevice.h>
  42. #include <linux/if_ether.h>
  43. #include <rdma/ib_verbs.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/ib_umem.h>
  46. #include <rdma/ib_addr.h>
  47. #include <rdma/ib_mad.h>
  48. #include <rdma/ib_cache.h>
  49. #include "bnxt_ulp.h"
  50. #include "roce_hsi.h"
  51. #include "qplib_res.h"
  52. #include "qplib_sp.h"
  53. #include "qplib_fp.h"
  54. #include "qplib_rcfw.h"
  55. #include "bnxt_re.h"
  56. #include "ib_verbs.h"
  57. #include <rdma/bnxt_re-abi.h>
  58. static int __from_ib_access_flags(int iflags)
  59. {
  60. int qflags = 0;
  61. if (iflags & IB_ACCESS_LOCAL_WRITE)
  62. qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  63. if (iflags & IB_ACCESS_REMOTE_READ)
  64. qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
  65. if (iflags & IB_ACCESS_REMOTE_WRITE)
  66. qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
  67. if (iflags & IB_ACCESS_REMOTE_ATOMIC)
  68. qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
  69. if (iflags & IB_ACCESS_MW_BIND)
  70. qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
  71. if (iflags & IB_ZERO_BASED)
  72. qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
  73. if (iflags & IB_ACCESS_ON_DEMAND)
  74. qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
  75. return qflags;
  76. };
  77. static enum ib_access_flags __to_ib_access_flags(int qflags)
  78. {
  79. enum ib_access_flags iflags = 0;
  80. if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
  81. iflags |= IB_ACCESS_LOCAL_WRITE;
  82. if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
  83. iflags |= IB_ACCESS_REMOTE_WRITE;
  84. if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
  85. iflags |= IB_ACCESS_REMOTE_READ;
  86. if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
  87. iflags |= IB_ACCESS_REMOTE_ATOMIC;
  88. if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
  89. iflags |= IB_ACCESS_MW_BIND;
  90. if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
  91. iflags |= IB_ZERO_BASED;
  92. if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
  93. iflags |= IB_ACCESS_ON_DEMAND;
  94. return iflags;
  95. };
  96. static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
  97. struct bnxt_qplib_sge *sg_list, int num)
  98. {
  99. int i, total = 0;
  100. for (i = 0; i < num; i++) {
  101. sg_list[i].addr = ib_sg_list[i].addr;
  102. sg_list[i].lkey = ib_sg_list[i].lkey;
  103. sg_list[i].size = ib_sg_list[i].length;
  104. total += sg_list[i].size;
  105. }
  106. return total;
  107. }
  108. /* Device */
  109. struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
  110. {
  111. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  112. struct net_device *netdev = NULL;
  113. rcu_read_lock();
  114. if (rdev)
  115. netdev = rdev->netdev;
  116. if (netdev)
  117. dev_hold(netdev);
  118. rcu_read_unlock();
  119. return netdev;
  120. }
  121. int bnxt_re_query_device(struct ib_device *ibdev,
  122. struct ib_device_attr *ib_attr,
  123. struct ib_udata *udata)
  124. {
  125. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  126. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  127. memset(ib_attr, 0, sizeof(*ib_attr));
  128. memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
  129. min(sizeof(dev_attr->fw_ver),
  130. sizeof(ib_attr->fw_ver)));
  131. bnxt_qplib_get_guid(rdev->netdev->dev_addr,
  132. (u8 *)&ib_attr->sys_image_guid);
  133. ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
  134. ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
  135. ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
  136. ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
  137. ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
  138. ib_attr->max_qp = dev_attr->max_qp;
  139. ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
  140. ib_attr->device_cap_flags =
  141. IB_DEVICE_CURR_QP_STATE_MOD
  142. | IB_DEVICE_RC_RNR_NAK_GEN
  143. | IB_DEVICE_SHUTDOWN_PORT
  144. | IB_DEVICE_SYS_IMAGE_GUID
  145. | IB_DEVICE_LOCAL_DMA_LKEY
  146. | IB_DEVICE_RESIZE_MAX_WR
  147. | IB_DEVICE_PORT_ACTIVE_EVENT
  148. | IB_DEVICE_N_NOTIFY_CQ
  149. | IB_DEVICE_MEM_WINDOW
  150. | IB_DEVICE_MEM_WINDOW_TYPE_2B
  151. | IB_DEVICE_MEM_MGT_EXTENSIONS;
  152. ib_attr->max_send_sge = dev_attr->max_qp_sges;
  153. ib_attr->max_recv_sge = dev_attr->max_qp_sges;
  154. ib_attr->max_sge_rd = dev_attr->max_qp_sges;
  155. ib_attr->max_cq = dev_attr->max_cq;
  156. ib_attr->max_cqe = dev_attr->max_cq_wqes;
  157. ib_attr->max_mr = dev_attr->max_mr;
  158. ib_attr->max_pd = dev_attr->max_pd;
  159. ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
  160. ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
  161. ib_attr->atomic_cap = IB_ATOMIC_NONE;
  162. ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
  163. ib_attr->max_ee_rd_atom = 0;
  164. ib_attr->max_res_rd_atom = 0;
  165. ib_attr->max_ee_init_rd_atom = 0;
  166. ib_attr->max_ee = 0;
  167. ib_attr->max_rdd = 0;
  168. ib_attr->max_mw = dev_attr->max_mw;
  169. ib_attr->max_raw_ipv6_qp = 0;
  170. ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
  171. ib_attr->max_mcast_grp = 0;
  172. ib_attr->max_mcast_qp_attach = 0;
  173. ib_attr->max_total_mcast_qp_attach = 0;
  174. ib_attr->max_ah = dev_attr->max_ah;
  175. ib_attr->max_fmr = 0;
  176. ib_attr->max_map_per_fmr = 0;
  177. ib_attr->max_srq = dev_attr->max_srq;
  178. ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
  179. ib_attr->max_srq_sge = dev_attr->max_srq_sges;
  180. ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
  181. ib_attr->max_pkeys = 1;
  182. ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
  183. return 0;
  184. }
  185. int bnxt_re_modify_device(struct ib_device *ibdev,
  186. int device_modify_mask,
  187. struct ib_device_modify *device_modify)
  188. {
  189. switch (device_modify_mask) {
  190. case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
  191. /* Modify the GUID requires the modification of the GID table */
  192. /* GUID should be made as READ-ONLY */
  193. break;
  194. case IB_DEVICE_MODIFY_NODE_DESC:
  195. /* Node Desc should be made as READ-ONLY */
  196. break;
  197. default:
  198. break;
  199. }
  200. return 0;
  201. }
  202. /* Port */
  203. int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
  204. struct ib_port_attr *port_attr)
  205. {
  206. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  207. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  208. memset(port_attr, 0, sizeof(*port_attr));
  209. if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
  210. port_attr->state = IB_PORT_ACTIVE;
  211. port_attr->phys_state = 5;
  212. } else {
  213. port_attr->state = IB_PORT_DOWN;
  214. port_attr->phys_state = 3;
  215. }
  216. port_attr->max_mtu = IB_MTU_4096;
  217. port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
  218. port_attr->gid_tbl_len = dev_attr->max_sgid;
  219. port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  220. IB_PORT_DEVICE_MGMT_SUP |
  221. IB_PORT_VENDOR_CLASS_SUP;
  222. port_attr->ip_gids = true;
  223. port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
  224. port_attr->bad_pkey_cntr = 0;
  225. port_attr->qkey_viol_cntr = 0;
  226. port_attr->pkey_tbl_len = dev_attr->max_pkey;
  227. port_attr->lid = 0;
  228. port_attr->sm_lid = 0;
  229. port_attr->lmc = 0;
  230. port_attr->max_vl_num = 4;
  231. port_attr->sm_sl = 0;
  232. port_attr->subnet_timeout = 0;
  233. port_attr->init_type_reply = 0;
  234. port_attr->active_speed = rdev->active_speed;
  235. port_attr->active_width = rdev->active_width;
  236. return 0;
  237. }
  238. int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
  239. struct ib_port_immutable *immutable)
  240. {
  241. struct ib_port_attr port_attr;
  242. if (bnxt_re_query_port(ibdev, port_num, &port_attr))
  243. return -EINVAL;
  244. immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
  245. immutable->gid_tbl_len = port_attr.gid_tbl_len;
  246. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  247. immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
  248. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  249. return 0;
  250. }
  251. void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
  252. {
  253. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  254. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
  255. rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
  256. rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
  257. }
  258. int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
  259. u16 index, u16 *pkey)
  260. {
  261. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  262. /* Ignore port_num */
  263. memset(pkey, 0, sizeof(*pkey));
  264. return bnxt_qplib_get_pkey(&rdev->qplib_res,
  265. &rdev->qplib_res.pkey_tbl, index, pkey);
  266. }
  267. int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
  268. int index, union ib_gid *gid)
  269. {
  270. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  271. int rc = 0;
  272. /* Ignore port_num */
  273. memset(gid, 0, sizeof(*gid));
  274. rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
  275. &rdev->qplib_res.sgid_tbl, index,
  276. (struct bnxt_qplib_gid *)gid);
  277. return rc;
  278. }
  279. int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
  280. {
  281. int rc = 0;
  282. struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
  283. struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
  284. struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
  285. struct bnxt_qplib_gid *gid_to_del;
  286. /* Delete the entry from the hardware */
  287. ctx = *context;
  288. if (!ctx)
  289. return -EINVAL;
  290. if (sgid_tbl && sgid_tbl->active) {
  291. if (ctx->idx >= sgid_tbl->max)
  292. return -EINVAL;
  293. gid_to_del = &sgid_tbl->tbl[ctx->idx];
  294. /* DEL_GID is called in WQ context(netdevice_event_work_handler)
  295. * or via the ib_unregister_device path. In the former case QP1
  296. * may not be destroyed yet, in which case just return as FW
  297. * needs that entry to be present and will fail it's deletion.
  298. * We could get invoked again after QP1 is destroyed OR get an
  299. * ADD_GID call with a different GID value for the same index
  300. * where we issue MODIFY_GID cmd to update the GID entry -- TBD
  301. */
  302. if (ctx->idx == 0 &&
  303. rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
  304. ctx->refcnt == 1 && rdev->qp1_sqp) {
  305. dev_dbg(rdev_to_dev(rdev),
  306. "Trying to delete GID0 while QP1 is alive\n");
  307. return -EFAULT;
  308. }
  309. ctx->refcnt--;
  310. if (!ctx->refcnt) {
  311. rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true);
  312. if (rc) {
  313. dev_err(rdev_to_dev(rdev),
  314. "Failed to remove GID: %#x", rc);
  315. } else {
  316. ctx_tbl = sgid_tbl->ctx;
  317. ctx_tbl[ctx->idx] = NULL;
  318. kfree(ctx);
  319. }
  320. }
  321. } else {
  322. return -EINVAL;
  323. }
  324. return rc;
  325. }
  326. int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
  327. {
  328. int rc;
  329. u32 tbl_idx = 0;
  330. u16 vlan_id = 0xFFFF;
  331. struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
  332. struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
  333. struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
  334. if ((attr->ndev) && is_vlan_dev(attr->ndev))
  335. vlan_id = vlan_dev_vlan_id(attr->ndev);
  336. rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
  337. rdev->qplib_res.netdev->dev_addr,
  338. vlan_id, true, &tbl_idx);
  339. if (rc == -EALREADY) {
  340. ctx_tbl = sgid_tbl->ctx;
  341. ctx_tbl[tbl_idx]->refcnt++;
  342. *context = ctx_tbl[tbl_idx];
  343. return 0;
  344. }
  345. if (rc < 0) {
  346. dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
  347. return rc;
  348. }
  349. ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
  350. if (!ctx)
  351. return -ENOMEM;
  352. ctx_tbl = sgid_tbl->ctx;
  353. ctx->idx = tbl_idx;
  354. ctx->refcnt = 1;
  355. ctx_tbl[tbl_idx] = ctx;
  356. *context = ctx;
  357. return rc;
  358. }
  359. enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
  360. u8 port_num)
  361. {
  362. return IB_LINK_LAYER_ETHERNET;
  363. }
  364. #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
  365. static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
  366. {
  367. struct bnxt_re_fence_data *fence = &pd->fence;
  368. struct ib_mr *ib_mr = &fence->mr->ib_mr;
  369. struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
  370. memset(wqe, 0, sizeof(*wqe));
  371. wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
  372. wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
  373. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  374. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  375. wqe->bind.zero_based = false;
  376. wqe->bind.parent_l_key = ib_mr->lkey;
  377. wqe->bind.va = (u64)(unsigned long)fence->va;
  378. wqe->bind.length = fence->size;
  379. wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
  380. wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
  381. /* Save the initial rkey in fence structure for now;
  382. * wqe->bind.r_key will be set at (re)bind time.
  383. */
  384. fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
  385. }
  386. static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
  387. {
  388. struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
  389. qplib_qp);
  390. struct ib_pd *ib_pd = qp->ib_qp.pd;
  391. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  392. struct bnxt_re_fence_data *fence = &pd->fence;
  393. struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
  394. struct bnxt_qplib_swqe wqe;
  395. int rc;
  396. memcpy(&wqe, fence_wqe, sizeof(wqe));
  397. wqe.bind.r_key = fence->bind_rkey;
  398. fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
  399. dev_dbg(rdev_to_dev(qp->rdev),
  400. "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
  401. wqe.bind.r_key, qp->qplib_qp.id, pd);
  402. rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
  403. if (rc) {
  404. dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
  405. return rc;
  406. }
  407. bnxt_qplib_post_send_db(&qp->qplib_qp);
  408. return rc;
  409. }
  410. static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
  411. {
  412. struct bnxt_re_fence_data *fence = &pd->fence;
  413. struct bnxt_re_dev *rdev = pd->rdev;
  414. struct device *dev = &rdev->en_dev->pdev->dev;
  415. struct bnxt_re_mr *mr = fence->mr;
  416. if (fence->mw) {
  417. bnxt_re_dealloc_mw(fence->mw);
  418. fence->mw = NULL;
  419. }
  420. if (mr) {
  421. if (mr->ib_mr.rkey)
  422. bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
  423. true);
  424. if (mr->ib_mr.lkey)
  425. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  426. kfree(mr);
  427. fence->mr = NULL;
  428. }
  429. if (fence->dma_addr) {
  430. dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
  431. DMA_BIDIRECTIONAL);
  432. fence->dma_addr = 0;
  433. }
  434. }
  435. static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
  436. {
  437. int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
  438. struct bnxt_re_fence_data *fence = &pd->fence;
  439. struct bnxt_re_dev *rdev = pd->rdev;
  440. struct device *dev = &rdev->en_dev->pdev->dev;
  441. struct bnxt_re_mr *mr = NULL;
  442. dma_addr_t dma_addr = 0;
  443. struct ib_mw *mw;
  444. u64 pbl_tbl;
  445. int rc;
  446. dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
  447. DMA_BIDIRECTIONAL);
  448. rc = dma_mapping_error(dev, dma_addr);
  449. if (rc) {
  450. dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
  451. rc = -EIO;
  452. fence->dma_addr = 0;
  453. goto fail;
  454. }
  455. fence->dma_addr = dma_addr;
  456. /* Allocate a MR */
  457. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  458. if (!mr) {
  459. rc = -ENOMEM;
  460. goto fail;
  461. }
  462. fence->mr = mr;
  463. mr->rdev = rdev;
  464. mr->qplib_mr.pd = &pd->qplib_pd;
  465. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
  466. mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
  467. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  468. if (rc) {
  469. dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
  470. goto fail;
  471. }
  472. /* Register MR */
  473. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  474. mr->qplib_mr.va = (u64)(unsigned long)fence->va;
  475. mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
  476. pbl_tbl = dma_addr;
  477. rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
  478. BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE);
  479. if (rc) {
  480. dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
  481. goto fail;
  482. }
  483. mr->ib_mr.rkey = mr->qplib_mr.rkey;
  484. /* Create a fence MW only for kernel consumers */
  485. mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
  486. if (IS_ERR(mw)) {
  487. dev_err(rdev_to_dev(rdev),
  488. "Failed to create fence-MW for PD: %p\n", pd);
  489. rc = PTR_ERR(mw);
  490. goto fail;
  491. }
  492. fence->mw = mw;
  493. bnxt_re_create_fence_wqe(pd);
  494. return 0;
  495. fail:
  496. bnxt_re_destroy_fence_mr(pd);
  497. return rc;
  498. }
  499. /* Protection Domains */
  500. int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
  501. {
  502. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  503. struct bnxt_re_dev *rdev = pd->rdev;
  504. int rc;
  505. bnxt_re_destroy_fence_mr(pd);
  506. if (pd->qplib_pd.id) {
  507. rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res,
  508. &rdev->qplib_res.pd_tbl,
  509. &pd->qplib_pd);
  510. if (rc)
  511. dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD");
  512. }
  513. kfree(pd);
  514. return 0;
  515. }
  516. struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev,
  517. struct ib_ucontext *ucontext,
  518. struct ib_udata *udata)
  519. {
  520. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  521. struct bnxt_re_ucontext *ucntx = container_of(ucontext,
  522. struct bnxt_re_ucontext,
  523. ib_uctx);
  524. struct bnxt_re_pd *pd;
  525. int rc;
  526. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  527. if (!pd)
  528. return ERR_PTR(-ENOMEM);
  529. pd->rdev = rdev;
  530. if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
  531. dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
  532. rc = -ENOMEM;
  533. goto fail;
  534. }
  535. if (udata) {
  536. struct bnxt_re_pd_resp resp;
  537. if (!ucntx->dpi.dbr) {
  538. /* Allocate DPI in alloc_pd to avoid failing of
  539. * ibv_devinfo and family of application when DPIs
  540. * are depleted.
  541. */
  542. if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
  543. &ucntx->dpi, ucntx)) {
  544. rc = -ENOMEM;
  545. goto dbfail;
  546. }
  547. }
  548. resp.pdid = pd->qplib_pd.id;
  549. /* Still allow mapping this DBR to the new user PD. */
  550. resp.dpi = ucntx->dpi.dpi;
  551. resp.dbr = (u64)ucntx->dpi.umdbr;
  552. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  553. if (rc) {
  554. dev_err(rdev_to_dev(rdev),
  555. "Failed to copy user response\n");
  556. goto dbfail;
  557. }
  558. }
  559. if (!udata)
  560. if (bnxt_re_create_fence_mr(pd))
  561. dev_warn(rdev_to_dev(rdev),
  562. "Failed to create Fence-MR\n");
  563. return &pd->ib_pd;
  564. dbfail:
  565. (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
  566. &pd->qplib_pd);
  567. fail:
  568. kfree(pd);
  569. return ERR_PTR(rc);
  570. }
  571. /* Address Handles */
  572. int bnxt_re_destroy_ah(struct ib_ah *ib_ah)
  573. {
  574. struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
  575. struct bnxt_re_dev *rdev = ah->rdev;
  576. int rc;
  577. rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah);
  578. if (rc) {
  579. dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH");
  580. return rc;
  581. }
  582. kfree(ah);
  583. return 0;
  584. }
  585. struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
  586. struct rdma_ah_attr *ah_attr,
  587. struct ib_udata *udata)
  588. {
  589. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  590. struct bnxt_re_dev *rdev = pd->rdev;
  591. struct bnxt_re_ah *ah;
  592. const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
  593. int rc;
  594. u8 nw_type;
  595. if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
  596. dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
  597. return ERR_PTR(-EINVAL);
  598. }
  599. ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
  600. if (!ah)
  601. return ERR_PTR(-ENOMEM);
  602. ah->rdev = rdev;
  603. ah->qplib_ah.pd = &pd->qplib_pd;
  604. /* Supply the configuration for the HW */
  605. memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
  606. sizeof(union ib_gid));
  607. /*
  608. * If RoCE V2 is enabled, stack will have two entries for
  609. * each GID entry. Avoiding this duplicte entry in HW. Dividing
  610. * the GID index by 2 for RoCE V2
  611. */
  612. ah->qplib_ah.sgid_index = grh->sgid_index / 2;
  613. ah->qplib_ah.host_sgid_index = grh->sgid_index;
  614. ah->qplib_ah.traffic_class = grh->traffic_class;
  615. ah->qplib_ah.flow_label = grh->flow_label;
  616. ah->qplib_ah.hop_limit = grh->hop_limit;
  617. ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
  618. if (ib_pd->uobject &&
  619. !rdma_is_multicast_addr((struct in6_addr *)
  620. grh->dgid.raw) &&
  621. !rdma_link_local_addr((struct in6_addr *)
  622. grh->dgid.raw)) {
  623. const struct ib_gid_attr *sgid_attr;
  624. sgid_attr = grh->sgid_attr;
  625. /* Get network header type for this GID */
  626. nw_type = rdma_gid_attr_network_type(sgid_attr);
  627. switch (nw_type) {
  628. case RDMA_NETWORK_IPV4:
  629. ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
  630. break;
  631. case RDMA_NETWORK_IPV6:
  632. ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
  633. break;
  634. default:
  635. ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
  636. break;
  637. }
  638. }
  639. memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
  640. rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
  641. if (rc) {
  642. dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
  643. goto fail;
  644. }
  645. /* Write AVID to shared page. */
  646. if (ib_pd->uobject) {
  647. struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
  648. struct bnxt_re_ucontext *uctx;
  649. unsigned long flag;
  650. u32 *wrptr;
  651. uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
  652. spin_lock_irqsave(&uctx->sh_lock, flag);
  653. wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
  654. *wrptr = ah->qplib_ah.id;
  655. wmb(); /* make sure cache is updated. */
  656. spin_unlock_irqrestore(&uctx->sh_lock, flag);
  657. }
  658. return &ah->ib_ah;
  659. fail:
  660. kfree(ah);
  661. return ERR_PTR(rc);
  662. }
  663. int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
  664. {
  665. return 0;
  666. }
  667. int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
  668. {
  669. struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
  670. ah_attr->type = ib_ah->type;
  671. rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
  672. memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
  673. rdma_ah_set_grh(ah_attr, NULL, 0,
  674. ah->qplib_ah.host_sgid_index,
  675. 0, ah->qplib_ah.traffic_class);
  676. rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
  677. rdma_ah_set_port_num(ah_attr, 1);
  678. rdma_ah_set_static_rate(ah_attr, 0);
  679. return 0;
  680. }
  681. unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
  682. __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
  683. {
  684. unsigned long flags;
  685. spin_lock_irqsave(&qp->scq->cq_lock, flags);
  686. if (qp->rcq != qp->scq)
  687. spin_lock(&qp->rcq->cq_lock);
  688. else
  689. __acquire(&qp->rcq->cq_lock);
  690. return flags;
  691. }
  692. void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
  693. unsigned long flags)
  694. __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
  695. {
  696. if (qp->rcq != qp->scq)
  697. spin_unlock(&qp->rcq->cq_lock);
  698. else
  699. __release(&qp->rcq->cq_lock);
  700. spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
  701. }
  702. /* Queue Pairs */
  703. int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
  704. {
  705. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  706. struct bnxt_re_dev *rdev = qp->rdev;
  707. int rc;
  708. unsigned int flags;
  709. bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
  710. rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
  711. if (rc) {
  712. dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
  713. return rc;
  714. }
  715. flags = bnxt_re_lock_cqs(qp);
  716. bnxt_qplib_clean_qp(&qp->qplib_qp);
  717. bnxt_re_unlock_cqs(qp, flags);
  718. bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
  719. if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
  720. rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
  721. &rdev->sqp_ah->qplib_ah);
  722. if (rc) {
  723. dev_err(rdev_to_dev(rdev),
  724. "Failed to destroy HW AH for shadow QP");
  725. return rc;
  726. }
  727. bnxt_qplib_clean_qp(&qp->qplib_qp);
  728. rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
  729. &rdev->qp1_sqp->qplib_qp);
  730. if (rc) {
  731. dev_err(rdev_to_dev(rdev),
  732. "Failed to destroy Shadow QP");
  733. return rc;
  734. }
  735. bnxt_qplib_free_qp_res(&rdev->qplib_res,
  736. &rdev->qp1_sqp->qplib_qp);
  737. mutex_lock(&rdev->qp_lock);
  738. list_del(&rdev->qp1_sqp->list);
  739. atomic_dec(&rdev->qp_count);
  740. mutex_unlock(&rdev->qp_lock);
  741. kfree(rdev->sqp_ah);
  742. kfree(rdev->qp1_sqp);
  743. rdev->qp1_sqp = NULL;
  744. rdev->sqp_ah = NULL;
  745. }
  746. if (!IS_ERR_OR_NULL(qp->rumem))
  747. ib_umem_release(qp->rumem);
  748. if (!IS_ERR_OR_NULL(qp->sumem))
  749. ib_umem_release(qp->sumem);
  750. mutex_lock(&rdev->qp_lock);
  751. list_del(&qp->list);
  752. atomic_dec(&rdev->qp_count);
  753. mutex_unlock(&rdev->qp_lock);
  754. kfree(qp);
  755. return 0;
  756. }
  757. static u8 __from_ib_qp_type(enum ib_qp_type type)
  758. {
  759. switch (type) {
  760. case IB_QPT_GSI:
  761. return CMDQ_CREATE_QP1_TYPE_GSI;
  762. case IB_QPT_RC:
  763. return CMDQ_CREATE_QP_TYPE_RC;
  764. case IB_QPT_UD:
  765. return CMDQ_CREATE_QP_TYPE_UD;
  766. default:
  767. return IB_QPT_MAX;
  768. }
  769. }
  770. static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
  771. struct bnxt_re_qp *qp, struct ib_udata *udata)
  772. {
  773. struct bnxt_re_qp_req ureq;
  774. struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
  775. struct ib_umem *umem;
  776. int bytes = 0;
  777. struct ib_ucontext *context = pd->ib_pd.uobject->context;
  778. struct bnxt_re_ucontext *cntx = container_of(context,
  779. struct bnxt_re_ucontext,
  780. ib_uctx);
  781. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  782. return -EFAULT;
  783. bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
  784. /* Consider mapping PSN search memory only for RC QPs. */
  785. if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
  786. bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
  787. bytes = PAGE_ALIGN(bytes);
  788. umem = ib_umem_get(context, ureq.qpsva, bytes,
  789. IB_ACCESS_LOCAL_WRITE, 1);
  790. if (IS_ERR(umem))
  791. return PTR_ERR(umem);
  792. qp->sumem = umem;
  793. qplib_qp->sq.sglist = umem->sg_head.sgl;
  794. qplib_qp->sq.nmap = umem->nmap;
  795. qplib_qp->qp_handle = ureq.qp_handle;
  796. if (!qp->qplib_qp.srq) {
  797. bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
  798. bytes = PAGE_ALIGN(bytes);
  799. umem = ib_umem_get(context, ureq.qprva, bytes,
  800. IB_ACCESS_LOCAL_WRITE, 1);
  801. if (IS_ERR(umem))
  802. goto rqfail;
  803. qp->rumem = umem;
  804. qplib_qp->rq.sglist = umem->sg_head.sgl;
  805. qplib_qp->rq.nmap = umem->nmap;
  806. }
  807. qplib_qp->dpi = &cntx->dpi;
  808. return 0;
  809. rqfail:
  810. ib_umem_release(qp->sumem);
  811. qp->sumem = NULL;
  812. qplib_qp->sq.sglist = NULL;
  813. qplib_qp->sq.nmap = 0;
  814. return PTR_ERR(umem);
  815. }
  816. static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
  817. (struct bnxt_re_pd *pd,
  818. struct bnxt_qplib_res *qp1_res,
  819. struct bnxt_qplib_qp *qp1_qp)
  820. {
  821. struct bnxt_re_dev *rdev = pd->rdev;
  822. struct bnxt_re_ah *ah;
  823. union ib_gid sgid;
  824. int rc;
  825. ah = kzalloc(sizeof(*ah), GFP_KERNEL);
  826. if (!ah)
  827. return NULL;
  828. ah->rdev = rdev;
  829. ah->qplib_ah.pd = &pd->qplib_pd;
  830. rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
  831. if (rc)
  832. goto fail;
  833. /* supply the dgid data same as sgid */
  834. memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
  835. sizeof(union ib_gid));
  836. ah->qplib_ah.sgid_index = 0;
  837. ah->qplib_ah.traffic_class = 0;
  838. ah->qplib_ah.flow_label = 0;
  839. ah->qplib_ah.hop_limit = 1;
  840. ah->qplib_ah.sl = 0;
  841. /* Have DMAC same as SMAC */
  842. ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
  843. rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
  844. if (rc) {
  845. dev_err(rdev_to_dev(rdev),
  846. "Failed to allocate HW AH for Shadow QP");
  847. goto fail;
  848. }
  849. return ah;
  850. fail:
  851. kfree(ah);
  852. return NULL;
  853. }
  854. static struct bnxt_re_qp *bnxt_re_create_shadow_qp
  855. (struct bnxt_re_pd *pd,
  856. struct bnxt_qplib_res *qp1_res,
  857. struct bnxt_qplib_qp *qp1_qp)
  858. {
  859. struct bnxt_re_dev *rdev = pd->rdev;
  860. struct bnxt_re_qp *qp;
  861. int rc;
  862. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  863. if (!qp)
  864. return NULL;
  865. qp->rdev = rdev;
  866. /* Initialize the shadow QP structure from the QP1 values */
  867. ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
  868. qp->qplib_qp.pd = &pd->qplib_pd;
  869. qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
  870. qp->qplib_qp.type = IB_QPT_UD;
  871. qp->qplib_qp.max_inline_data = 0;
  872. qp->qplib_qp.sig_type = true;
  873. /* Shadow QP SQ depth should be same as QP1 RQ depth */
  874. qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
  875. qp->qplib_qp.sq.max_sge = 2;
  876. /* Q full delta can be 1 since it is internal QP */
  877. qp->qplib_qp.sq.q_full_delta = 1;
  878. qp->qplib_qp.scq = qp1_qp->scq;
  879. qp->qplib_qp.rcq = qp1_qp->rcq;
  880. qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
  881. qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
  882. /* Q full delta can be 1 since it is internal QP */
  883. qp->qplib_qp.rq.q_full_delta = 1;
  884. qp->qplib_qp.mtu = qp1_qp->mtu;
  885. qp->qplib_qp.sq_hdr_buf_size = 0;
  886. qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
  887. qp->qplib_qp.dpi = &rdev->dpi_privileged;
  888. rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
  889. if (rc)
  890. goto fail;
  891. rdev->sqp_id = qp->qplib_qp.id;
  892. spin_lock_init(&qp->sq_lock);
  893. INIT_LIST_HEAD(&qp->list);
  894. mutex_lock(&rdev->qp_lock);
  895. list_add_tail(&qp->list, &rdev->qp_list);
  896. atomic_inc(&rdev->qp_count);
  897. mutex_unlock(&rdev->qp_lock);
  898. return qp;
  899. fail:
  900. kfree(qp);
  901. return NULL;
  902. }
  903. struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
  904. struct ib_qp_init_attr *qp_init_attr,
  905. struct ib_udata *udata)
  906. {
  907. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  908. struct bnxt_re_dev *rdev = pd->rdev;
  909. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  910. struct bnxt_re_qp *qp;
  911. struct bnxt_re_cq *cq;
  912. struct bnxt_re_srq *srq;
  913. int rc, entries;
  914. if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
  915. (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
  916. (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
  917. (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
  918. (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
  919. return ERR_PTR(-EINVAL);
  920. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  921. if (!qp)
  922. return ERR_PTR(-ENOMEM);
  923. qp->rdev = rdev;
  924. ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
  925. qp->qplib_qp.pd = &pd->qplib_pd;
  926. qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
  927. qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
  928. if (qp->qplib_qp.type == IB_QPT_MAX) {
  929. dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
  930. qp->qplib_qp.type);
  931. rc = -EINVAL;
  932. goto fail;
  933. }
  934. qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
  935. qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
  936. IB_SIGNAL_ALL_WR) ? true : false);
  937. qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
  938. if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
  939. qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
  940. if (qp_init_attr->send_cq) {
  941. cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
  942. ib_cq);
  943. if (!cq) {
  944. dev_err(rdev_to_dev(rdev), "Send CQ not found");
  945. rc = -EINVAL;
  946. goto fail;
  947. }
  948. qp->qplib_qp.scq = &cq->qplib_cq;
  949. qp->scq = cq;
  950. }
  951. if (qp_init_attr->recv_cq) {
  952. cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
  953. ib_cq);
  954. if (!cq) {
  955. dev_err(rdev_to_dev(rdev), "Receive CQ not found");
  956. rc = -EINVAL;
  957. goto fail;
  958. }
  959. qp->qplib_qp.rcq = &cq->qplib_cq;
  960. qp->rcq = cq;
  961. }
  962. if (qp_init_attr->srq) {
  963. srq = container_of(qp_init_attr->srq, struct bnxt_re_srq,
  964. ib_srq);
  965. if (!srq) {
  966. dev_err(rdev_to_dev(rdev), "SRQ not found");
  967. rc = -EINVAL;
  968. goto fail;
  969. }
  970. qp->qplib_qp.srq = &srq->qplib_srq;
  971. qp->qplib_qp.rq.max_wqe = 0;
  972. } else {
  973. /* Allocate 1 more than what's provided so posting max doesn't
  974. * mean empty
  975. */
  976. entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
  977. qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
  978. dev_attr->max_qp_wqes + 1);
  979. qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
  980. qp_init_attr->cap.max_recv_wr;
  981. qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
  982. if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
  983. qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
  984. }
  985. qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
  986. if (qp_init_attr->qp_type == IB_QPT_GSI) {
  987. /* Allocate 1 more than what's provided */
  988. entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
  989. qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
  990. dev_attr->max_qp_wqes + 1);
  991. qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
  992. qp_init_attr->cap.max_send_wr;
  993. qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
  994. if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
  995. qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
  996. qp->qplib_qp.sq.max_sge++;
  997. if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
  998. qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
  999. qp->qplib_qp.rq_hdr_buf_size =
  1000. BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
  1001. qp->qplib_qp.sq_hdr_buf_size =
  1002. BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
  1003. qp->qplib_qp.dpi = &rdev->dpi_privileged;
  1004. rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
  1005. if (rc) {
  1006. dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
  1007. goto fail;
  1008. }
  1009. /* Create a shadow QP to handle the QP1 traffic */
  1010. rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
  1011. &qp->qplib_qp);
  1012. if (!rdev->qp1_sqp) {
  1013. rc = -EINVAL;
  1014. dev_err(rdev_to_dev(rdev),
  1015. "Failed to create Shadow QP for QP1");
  1016. goto qp_destroy;
  1017. }
  1018. rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
  1019. &qp->qplib_qp);
  1020. if (!rdev->sqp_ah) {
  1021. bnxt_qplib_destroy_qp(&rdev->qplib_res,
  1022. &rdev->qp1_sqp->qplib_qp);
  1023. rc = -EINVAL;
  1024. dev_err(rdev_to_dev(rdev),
  1025. "Failed to create AH entry for ShadowQP");
  1026. goto qp_destroy;
  1027. }
  1028. } else {
  1029. /* Allocate 128 + 1 more than what's provided */
  1030. entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
  1031. BNXT_QPLIB_RESERVED_QP_WRS + 1);
  1032. qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
  1033. dev_attr->max_qp_wqes +
  1034. BNXT_QPLIB_RESERVED_QP_WRS + 1);
  1035. qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
  1036. /*
  1037. * Reserving one slot for Phantom WQE. Application can
  1038. * post one extra entry in this case. But allowing this to avoid
  1039. * unexpected Queue full condition
  1040. */
  1041. qp->qplib_qp.sq.q_full_delta -= 1;
  1042. qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
  1043. qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
  1044. if (udata) {
  1045. rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
  1046. if (rc)
  1047. goto fail;
  1048. } else {
  1049. qp->qplib_qp.dpi = &rdev->dpi_privileged;
  1050. }
  1051. rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
  1052. if (rc) {
  1053. dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
  1054. goto free_umem;
  1055. }
  1056. }
  1057. qp->ib_qp.qp_num = qp->qplib_qp.id;
  1058. spin_lock_init(&qp->sq_lock);
  1059. spin_lock_init(&qp->rq_lock);
  1060. if (udata) {
  1061. struct bnxt_re_qp_resp resp;
  1062. resp.qpid = qp->ib_qp.qp_num;
  1063. resp.rsvd = 0;
  1064. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  1065. if (rc) {
  1066. dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
  1067. goto qp_destroy;
  1068. }
  1069. }
  1070. INIT_LIST_HEAD(&qp->list);
  1071. mutex_lock(&rdev->qp_lock);
  1072. list_add_tail(&qp->list, &rdev->qp_list);
  1073. atomic_inc(&rdev->qp_count);
  1074. mutex_unlock(&rdev->qp_lock);
  1075. return &qp->ib_qp;
  1076. qp_destroy:
  1077. bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
  1078. free_umem:
  1079. if (udata) {
  1080. if (qp->rumem)
  1081. ib_umem_release(qp->rumem);
  1082. if (qp->sumem)
  1083. ib_umem_release(qp->sumem);
  1084. }
  1085. fail:
  1086. kfree(qp);
  1087. return ERR_PTR(rc);
  1088. }
  1089. static u8 __from_ib_qp_state(enum ib_qp_state state)
  1090. {
  1091. switch (state) {
  1092. case IB_QPS_RESET:
  1093. return CMDQ_MODIFY_QP_NEW_STATE_RESET;
  1094. case IB_QPS_INIT:
  1095. return CMDQ_MODIFY_QP_NEW_STATE_INIT;
  1096. case IB_QPS_RTR:
  1097. return CMDQ_MODIFY_QP_NEW_STATE_RTR;
  1098. case IB_QPS_RTS:
  1099. return CMDQ_MODIFY_QP_NEW_STATE_RTS;
  1100. case IB_QPS_SQD:
  1101. return CMDQ_MODIFY_QP_NEW_STATE_SQD;
  1102. case IB_QPS_SQE:
  1103. return CMDQ_MODIFY_QP_NEW_STATE_SQE;
  1104. case IB_QPS_ERR:
  1105. default:
  1106. return CMDQ_MODIFY_QP_NEW_STATE_ERR;
  1107. }
  1108. }
  1109. static enum ib_qp_state __to_ib_qp_state(u8 state)
  1110. {
  1111. switch (state) {
  1112. case CMDQ_MODIFY_QP_NEW_STATE_RESET:
  1113. return IB_QPS_RESET;
  1114. case CMDQ_MODIFY_QP_NEW_STATE_INIT:
  1115. return IB_QPS_INIT;
  1116. case CMDQ_MODIFY_QP_NEW_STATE_RTR:
  1117. return IB_QPS_RTR;
  1118. case CMDQ_MODIFY_QP_NEW_STATE_RTS:
  1119. return IB_QPS_RTS;
  1120. case CMDQ_MODIFY_QP_NEW_STATE_SQD:
  1121. return IB_QPS_SQD;
  1122. case CMDQ_MODIFY_QP_NEW_STATE_SQE:
  1123. return IB_QPS_SQE;
  1124. case CMDQ_MODIFY_QP_NEW_STATE_ERR:
  1125. default:
  1126. return IB_QPS_ERR;
  1127. }
  1128. }
  1129. static u32 __from_ib_mtu(enum ib_mtu mtu)
  1130. {
  1131. switch (mtu) {
  1132. case IB_MTU_256:
  1133. return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
  1134. case IB_MTU_512:
  1135. return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
  1136. case IB_MTU_1024:
  1137. return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
  1138. case IB_MTU_2048:
  1139. return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
  1140. case IB_MTU_4096:
  1141. return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
  1142. default:
  1143. return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
  1144. }
  1145. }
  1146. static enum ib_mtu __to_ib_mtu(u32 mtu)
  1147. {
  1148. switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
  1149. case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
  1150. return IB_MTU_256;
  1151. case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
  1152. return IB_MTU_512;
  1153. case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
  1154. return IB_MTU_1024;
  1155. case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
  1156. return IB_MTU_2048;
  1157. case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
  1158. return IB_MTU_4096;
  1159. default:
  1160. return IB_MTU_2048;
  1161. }
  1162. }
  1163. /* Shared Receive Queues */
  1164. int bnxt_re_destroy_srq(struct ib_srq *ib_srq)
  1165. {
  1166. struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
  1167. ib_srq);
  1168. struct bnxt_re_dev *rdev = srq->rdev;
  1169. struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
  1170. struct bnxt_qplib_nq *nq = NULL;
  1171. int rc;
  1172. if (qplib_srq->cq)
  1173. nq = qplib_srq->cq->nq;
  1174. rc = bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
  1175. if (rc) {
  1176. dev_err(rdev_to_dev(rdev), "Destroy HW SRQ failed!");
  1177. return rc;
  1178. }
  1179. if (srq->umem)
  1180. ib_umem_release(srq->umem);
  1181. kfree(srq);
  1182. atomic_dec(&rdev->srq_count);
  1183. if (nq)
  1184. nq->budget--;
  1185. return 0;
  1186. }
  1187. static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
  1188. struct bnxt_re_pd *pd,
  1189. struct bnxt_re_srq *srq,
  1190. struct ib_udata *udata)
  1191. {
  1192. struct bnxt_re_srq_req ureq;
  1193. struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
  1194. struct ib_umem *umem;
  1195. int bytes = 0;
  1196. struct ib_ucontext *context = pd->ib_pd.uobject->context;
  1197. struct bnxt_re_ucontext *cntx = container_of(context,
  1198. struct bnxt_re_ucontext,
  1199. ib_uctx);
  1200. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1201. return -EFAULT;
  1202. bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
  1203. bytes = PAGE_ALIGN(bytes);
  1204. umem = ib_umem_get(context, ureq.srqva, bytes,
  1205. IB_ACCESS_LOCAL_WRITE, 1);
  1206. if (IS_ERR(umem))
  1207. return PTR_ERR(umem);
  1208. srq->umem = umem;
  1209. qplib_srq->nmap = umem->nmap;
  1210. qplib_srq->sglist = umem->sg_head.sgl;
  1211. qplib_srq->srq_handle = ureq.srq_handle;
  1212. qplib_srq->dpi = &cntx->dpi;
  1213. return 0;
  1214. }
  1215. struct ib_srq *bnxt_re_create_srq(struct ib_pd *ib_pd,
  1216. struct ib_srq_init_attr *srq_init_attr,
  1217. struct ib_udata *udata)
  1218. {
  1219. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  1220. struct bnxt_re_dev *rdev = pd->rdev;
  1221. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  1222. struct bnxt_re_srq *srq;
  1223. struct bnxt_qplib_nq *nq = NULL;
  1224. int rc, entries;
  1225. if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
  1226. dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded");
  1227. rc = -EINVAL;
  1228. goto exit;
  1229. }
  1230. if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
  1231. rc = -EOPNOTSUPP;
  1232. goto exit;
  1233. }
  1234. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1235. if (!srq) {
  1236. rc = -ENOMEM;
  1237. goto exit;
  1238. }
  1239. srq->rdev = rdev;
  1240. srq->qplib_srq.pd = &pd->qplib_pd;
  1241. srq->qplib_srq.dpi = &rdev->dpi_privileged;
  1242. /* Allocate 1 more than what's provided so posting max doesn't
  1243. * mean empty
  1244. */
  1245. entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
  1246. if (entries > dev_attr->max_srq_wqes + 1)
  1247. entries = dev_attr->max_srq_wqes + 1;
  1248. srq->qplib_srq.max_wqe = entries;
  1249. srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
  1250. srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
  1251. srq->srq_limit = srq_init_attr->attr.srq_limit;
  1252. srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
  1253. nq = &rdev->nq[0];
  1254. if (udata) {
  1255. rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
  1256. if (rc)
  1257. goto fail;
  1258. }
  1259. rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
  1260. if (rc) {
  1261. dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!");
  1262. goto fail;
  1263. }
  1264. if (udata) {
  1265. struct bnxt_re_srq_resp resp;
  1266. resp.srqid = srq->qplib_srq.id;
  1267. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  1268. if (rc) {
  1269. dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!");
  1270. bnxt_qplib_destroy_srq(&rdev->qplib_res,
  1271. &srq->qplib_srq);
  1272. goto fail;
  1273. }
  1274. }
  1275. if (nq)
  1276. nq->budget++;
  1277. atomic_inc(&rdev->srq_count);
  1278. return &srq->ib_srq;
  1279. fail:
  1280. if (srq->umem)
  1281. ib_umem_release(srq->umem);
  1282. kfree(srq);
  1283. exit:
  1284. return ERR_PTR(rc);
  1285. }
  1286. int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
  1287. enum ib_srq_attr_mask srq_attr_mask,
  1288. struct ib_udata *udata)
  1289. {
  1290. struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
  1291. ib_srq);
  1292. struct bnxt_re_dev *rdev = srq->rdev;
  1293. int rc;
  1294. switch (srq_attr_mask) {
  1295. case IB_SRQ_MAX_WR:
  1296. /* SRQ resize is not supported */
  1297. break;
  1298. case IB_SRQ_LIMIT:
  1299. /* Change the SRQ threshold */
  1300. if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
  1301. return -EINVAL;
  1302. srq->qplib_srq.threshold = srq_attr->srq_limit;
  1303. rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
  1304. if (rc) {
  1305. dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!");
  1306. return rc;
  1307. }
  1308. /* On success, update the shadow */
  1309. srq->srq_limit = srq_attr->srq_limit;
  1310. /* No need to Build and send response back to udata */
  1311. break;
  1312. default:
  1313. dev_err(rdev_to_dev(rdev),
  1314. "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
  1315. return -EINVAL;
  1316. }
  1317. return 0;
  1318. }
  1319. int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
  1320. {
  1321. struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
  1322. ib_srq);
  1323. struct bnxt_re_srq tsrq;
  1324. struct bnxt_re_dev *rdev = srq->rdev;
  1325. int rc;
  1326. /* Get live SRQ attr */
  1327. tsrq.qplib_srq.id = srq->qplib_srq.id;
  1328. rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
  1329. if (rc) {
  1330. dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!");
  1331. return rc;
  1332. }
  1333. srq_attr->max_wr = srq->qplib_srq.max_wqe;
  1334. srq_attr->max_sge = srq->qplib_srq.max_sge;
  1335. srq_attr->srq_limit = tsrq.qplib_srq.threshold;
  1336. return 0;
  1337. }
  1338. int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
  1339. const struct ib_recv_wr **bad_wr)
  1340. {
  1341. struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
  1342. ib_srq);
  1343. struct bnxt_qplib_swqe wqe;
  1344. unsigned long flags;
  1345. int rc = 0;
  1346. spin_lock_irqsave(&srq->lock, flags);
  1347. while (wr) {
  1348. /* Transcribe each ib_recv_wr to qplib_swqe */
  1349. wqe.num_sge = wr->num_sge;
  1350. bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
  1351. wqe.wr_id = wr->wr_id;
  1352. wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
  1353. rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
  1354. if (rc) {
  1355. *bad_wr = wr;
  1356. break;
  1357. }
  1358. wr = wr->next;
  1359. }
  1360. spin_unlock_irqrestore(&srq->lock, flags);
  1361. return rc;
  1362. }
  1363. static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
  1364. struct bnxt_re_qp *qp1_qp,
  1365. int qp_attr_mask)
  1366. {
  1367. struct bnxt_re_qp *qp = rdev->qp1_sqp;
  1368. int rc = 0;
  1369. if (qp_attr_mask & IB_QP_STATE) {
  1370. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
  1371. qp->qplib_qp.state = qp1_qp->qplib_qp.state;
  1372. }
  1373. if (qp_attr_mask & IB_QP_PKEY_INDEX) {
  1374. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
  1375. qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
  1376. }
  1377. if (qp_attr_mask & IB_QP_QKEY) {
  1378. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
  1379. /* Using a Random QKEY */
  1380. qp->qplib_qp.qkey = 0x81818181;
  1381. }
  1382. if (qp_attr_mask & IB_QP_SQ_PSN) {
  1383. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
  1384. qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
  1385. }
  1386. rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
  1387. if (rc)
  1388. dev_err(rdev_to_dev(rdev),
  1389. "Failed to modify Shadow QP for QP1");
  1390. return rc;
  1391. }
  1392. int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
  1393. int qp_attr_mask, struct ib_udata *udata)
  1394. {
  1395. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  1396. struct bnxt_re_dev *rdev = qp->rdev;
  1397. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  1398. enum ib_qp_state curr_qp_state, new_qp_state;
  1399. int rc, entries;
  1400. unsigned int flags;
  1401. u8 nw_type;
  1402. qp->qplib_qp.modify_flags = 0;
  1403. if (qp_attr_mask & IB_QP_STATE) {
  1404. curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
  1405. new_qp_state = qp_attr->qp_state;
  1406. if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
  1407. ib_qp->qp_type, qp_attr_mask,
  1408. IB_LINK_LAYER_ETHERNET)) {
  1409. dev_err(rdev_to_dev(rdev),
  1410. "Invalid attribute mask: %#x specified ",
  1411. qp_attr_mask);
  1412. dev_err(rdev_to_dev(rdev),
  1413. "for qpn: %#x type: %#x",
  1414. ib_qp->qp_num, ib_qp->qp_type);
  1415. dev_err(rdev_to_dev(rdev),
  1416. "curr_qp_state=0x%x, new_qp_state=0x%x\n",
  1417. curr_qp_state, new_qp_state);
  1418. return -EINVAL;
  1419. }
  1420. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
  1421. qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
  1422. if (!qp->sumem &&
  1423. qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
  1424. dev_dbg(rdev_to_dev(rdev),
  1425. "Move QP = %p to flush list\n",
  1426. qp);
  1427. flags = bnxt_re_lock_cqs(qp);
  1428. bnxt_qplib_add_flush_qp(&qp->qplib_qp);
  1429. bnxt_re_unlock_cqs(qp, flags);
  1430. }
  1431. if (!qp->sumem &&
  1432. qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
  1433. dev_dbg(rdev_to_dev(rdev),
  1434. "Move QP = %p out of flush list\n",
  1435. qp);
  1436. flags = bnxt_re_lock_cqs(qp);
  1437. bnxt_qplib_clean_qp(&qp->qplib_qp);
  1438. bnxt_re_unlock_cqs(qp, flags);
  1439. }
  1440. }
  1441. if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
  1442. qp->qplib_qp.modify_flags |=
  1443. CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
  1444. qp->qplib_qp.en_sqd_async_notify = true;
  1445. }
  1446. if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
  1447. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
  1448. qp->qplib_qp.access =
  1449. __from_ib_access_flags(qp_attr->qp_access_flags);
  1450. /* LOCAL_WRITE access must be set to allow RC receive */
  1451. qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  1452. }
  1453. if (qp_attr_mask & IB_QP_PKEY_INDEX) {
  1454. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
  1455. qp->qplib_qp.pkey_index = qp_attr->pkey_index;
  1456. }
  1457. if (qp_attr_mask & IB_QP_QKEY) {
  1458. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
  1459. qp->qplib_qp.qkey = qp_attr->qkey;
  1460. }
  1461. if (qp_attr_mask & IB_QP_AV) {
  1462. const struct ib_global_route *grh =
  1463. rdma_ah_read_grh(&qp_attr->ah_attr);
  1464. const struct ib_gid_attr *sgid_attr;
  1465. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
  1466. CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
  1467. CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
  1468. CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
  1469. CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
  1470. CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
  1471. CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
  1472. memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
  1473. sizeof(qp->qplib_qp.ah.dgid.data));
  1474. qp->qplib_qp.ah.flow_label = grh->flow_label;
  1475. /* If RoCE V2 is enabled, stack will have two entries for
  1476. * each GID entry. Avoiding this duplicte entry in HW. Dividing
  1477. * the GID index by 2 for RoCE V2
  1478. */
  1479. qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
  1480. qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
  1481. qp->qplib_qp.ah.hop_limit = grh->hop_limit;
  1482. qp->qplib_qp.ah.traffic_class = grh->traffic_class;
  1483. qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
  1484. ether_addr_copy(qp->qplib_qp.ah.dmac,
  1485. qp_attr->ah_attr.roce.dmac);
  1486. sgid_attr = qp_attr->ah_attr.grh.sgid_attr;
  1487. memcpy(qp->qplib_qp.smac, sgid_attr->ndev->dev_addr,
  1488. ETH_ALEN);
  1489. nw_type = rdma_gid_attr_network_type(sgid_attr);
  1490. switch (nw_type) {
  1491. case RDMA_NETWORK_IPV4:
  1492. qp->qplib_qp.nw_type =
  1493. CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
  1494. break;
  1495. case RDMA_NETWORK_IPV6:
  1496. qp->qplib_qp.nw_type =
  1497. CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
  1498. break;
  1499. default:
  1500. qp->qplib_qp.nw_type =
  1501. CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
  1502. break;
  1503. }
  1504. }
  1505. if (qp_attr_mask & IB_QP_PATH_MTU) {
  1506. qp->qplib_qp.modify_flags |=
  1507. CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
  1508. qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
  1509. qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
  1510. } else if (qp_attr->qp_state == IB_QPS_RTR) {
  1511. qp->qplib_qp.modify_flags |=
  1512. CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
  1513. qp->qplib_qp.path_mtu =
  1514. __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
  1515. qp->qplib_qp.mtu =
  1516. ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
  1517. }
  1518. if (qp_attr_mask & IB_QP_TIMEOUT) {
  1519. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
  1520. qp->qplib_qp.timeout = qp_attr->timeout;
  1521. }
  1522. if (qp_attr_mask & IB_QP_RETRY_CNT) {
  1523. qp->qplib_qp.modify_flags |=
  1524. CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
  1525. qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
  1526. }
  1527. if (qp_attr_mask & IB_QP_RNR_RETRY) {
  1528. qp->qplib_qp.modify_flags |=
  1529. CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
  1530. qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
  1531. }
  1532. if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
  1533. qp->qplib_qp.modify_flags |=
  1534. CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
  1535. qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
  1536. }
  1537. if (qp_attr_mask & IB_QP_RQ_PSN) {
  1538. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
  1539. qp->qplib_qp.rq.psn = qp_attr->rq_psn;
  1540. }
  1541. if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
  1542. qp->qplib_qp.modify_flags |=
  1543. CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
  1544. /* Cap the max_rd_atomic to device max */
  1545. qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
  1546. dev_attr->max_qp_rd_atom);
  1547. }
  1548. if (qp_attr_mask & IB_QP_SQ_PSN) {
  1549. qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
  1550. qp->qplib_qp.sq.psn = qp_attr->sq_psn;
  1551. }
  1552. if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
  1553. if (qp_attr->max_dest_rd_atomic >
  1554. dev_attr->max_qp_init_rd_atom) {
  1555. dev_err(rdev_to_dev(rdev),
  1556. "max_dest_rd_atomic requested%d is > dev_max%d",
  1557. qp_attr->max_dest_rd_atomic,
  1558. dev_attr->max_qp_init_rd_atom);
  1559. return -EINVAL;
  1560. }
  1561. qp->qplib_qp.modify_flags |=
  1562. CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
  1563. qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
  1564. }
  1565. if (qp_attr_mask & IB_QP_CAP) {
  1566. qp->qplib_qp.modify_flags |=
  1567. CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
  1568. CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
  1569. CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
  1570. CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
  1571. CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
  1572. if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
  1573. (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
  1574. (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
  1575. (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
  1576. (qp_attr->cap.max_inline_data >=
  1577. dev_attr->max_inline_data)) {
  1578. dev_err(rdev_to_dev(rdev),
  1579. "Create QP failed - max exceeded");
  1580. return -EINVAL;
  1581. }
  1582. entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
  1583. qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
  1584. dev_attr->max_qp_wqes + 1);
  1585. qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
  1586. qp_attr->cap.max_send_wr;
  1587. /*
  1588. * Reserving one slot for Phantom WQE. Some application can
  1589. * post one extra entry in this case. Allowing this to avoid
  1590. * unexpected Queue full condition
  1591. */
  1592. qp->qplib_qp.sq.q_full_delta -= 1;
  1593. qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
  1594. if (qp->qplib_qp.rq.max_wqe) {
  1595. entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
  1596. qp->qplib_qp.rq.max_wqe =
  1597. min_t(u32, entries, dev_attr->max_qp_wqes + 1);
  1598. qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
  1599. qp_attr->cap.max_recv_wr;
  1600. qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
  1601. } else {
  1602. /* SRQ was used prior, just ignore the RQ caps */
  1603. }
  1604. }
  1605. if (qp_attr_mask & IB_QP_DEST_QPN) {
  1606. qp->qplib_qp.modify_flags |=
  1607. CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
  1608. qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
  1609. }
  1610. rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
  1611. if (rc) {
  1612. dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
  1613. return rc;
  1614. }
  1615. if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
  1616. rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
  1617. return rc;
  1618. }
  1619. int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
  1620. int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1621. {
  1622. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  1623. struct bnxt_re_dev *rdev = qp->rdev;
  1624. struct bnxt_qplib_qp *qplib_qp;
  1625. int rc;
  1626. qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
  1627. if (!qplib_qp)
  1628. return -ENOMEM;
  1629. qplib_qp->id = qp->qplib_qp.id;
  1630. qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
  1631. rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
  1632. if (rc) {
  1633. dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
  1634. goto out;
  1635. }
  1636. qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
  1637. qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
  1638. qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
  1639. qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
  1640. qp_attr->pkey_index = qplib_qp->pkey_index;
  1641. qp_attr->qkey = qplib_qp->qkey;
  1642. qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
  1643. rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
  1644. qplib_qp->ah.host_sgid_index,
  1645. qplib_qp->ah.hop_limit,
  1646. qplib_qp->ah.traffic_class);
  1647. rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
  1648. rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
  1649. ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
  1650. qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
  1651. qp_attr->timeout = qplib_qp->timeout;
  1652. qp_attr->retry_cnt = qplib_qp->retry_cnt;
  1653. qp_attr->rnr_retry = qplib_qp->rnr_retry;
  1654. qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
  1655. qp_attr->rq_psn = qplib_qp->rq.psn;
  1656. qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
  1657. qp_attr->sq_psn = qplib_qp->sq.psn;
  1658. qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
  1659. qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
  1660. IB_SIGNAL_REQ_WR;
  1661. qp_attr->dest_qp_num = qplib_qp->dest_qpn;
  1662. qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
  1663. qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
  1664. qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
  1665. qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
  1666. qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
  1667. qp_init_attr->cap = qp_attr->cap;
  1668. out:
  1669. kfree(qplib_qp);
  1670. return rc;
  1671. }
  1672. /* Routine for sending QP1 packets for RoCE V1 an V2
  1673. */
  1674. static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
  1675. const struct ib_send_wr *wr,
  1676. struct bnxt_qplib_swqe *wqe,
  1677. int payload_size)
  1678. {
  1679. struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
  1680. ib_ah);
  1681. struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
  1682. const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
  1683. struct bnxt_qplib_sge sge;
  1684. u8 nw_type;
  1685. u16 ether_type;
  1686. union ib_gid dgid;
  1687. bool is_eth = false;
  1688. bool is_vlan = false;
  1689. bool is_grh = false;
  1690. bool is_udp = false;
  1691. u8 ip_version = 0;
  1692. u16 vlan_id = 0xFFFF;
  1693. void *buf;
  1694. int i, rc = 0;
  1695. memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
  1696. if (is_vlan_dev(sgid_attr->ndev))
  1697. vlan_id = vlan_dev_vlan_id(sgid_attr->ndev);
  1698. /* Get network header type for this GID */
  1699. nw_type = rdma_gid_attr_network_type(sgid_attr);
  1700. switch (nw_type) {
  1701. case RDMA_NETWORK_IPV4:
  1702. nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
  1703. break;
  1704. case RDMA_NETWORK_IPV6:
  1705. nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
  1706. break;
  1707. default:
  1708. nw_type = BNXT_RE_ROCE_V1_PACKET;
  1709. break;
  1710. }
  1711. memcpy(&dgid.raw, &qplib_ah->dgid, 16);
  1712. is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
  1713. if (is_udp) {
  1714. if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
  1715. ip_version = 4;
  1716. ether_type = ETH_P_IP;
  1717. } else {
  1718. ip_version = 6;
  1719. ether_type = ETH_P_IPV6;
  1720. }
  1721. is_grh = false;
  1722. } else {
  1723. ether_type = ETH_P_IBOE;
  1724. is_grh = true;
  1725. }
  1726. is_eth = true;
  1727. is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
  1728. ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
  1729. ip_version, is_udp, 0, &qp->qp1_hdr);
  1730. /* ETH */
  1731. ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
  1732. ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
  1733. /* For vlan, check the sgid for vlan existence */
  1734. if (!is_vlan) {
  1735. qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
  1736. } else {
  1737. qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
  1738. qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
  1739. }
  1740. if (is_grh || (ip_version == 6)) {
  1741. memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
  1742. sizeof(sgid_attr->gid));
  1743. memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
  1744. sizeof(sgid_attr->gid));
  1745. qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
  1746. }
  1747. if (ip_version == 4) {
  1748. qp->qp1_hdr.ip4.tos = 0;
  1749. qp->qp1_hdr.ip4.id = 0;
  1750. qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
  1751. qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
  1752. memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
  1753. memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
  1754. qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
  1755. }
  1756. if (is_udp) {
  1757. qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
  1758. qp->qp1_hdr.udp.sport = htons(0x8CD1);
  1759. qp->qp1_hdr.udp.csum = 0;
  1760. }
  1761. /* BTH */
  1762. if (wr->opcode == IB_WR_SEND_WITH_IMM) {
  1763. qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
  1764. qp->qp1_hdr.immediate_present = 1;
  1765. } else {
  1766. qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
  1767. }
  1768. if (wr->send_flags & IB_SEND_SOLICITED)
  1769. qp->qp1_hdr.bth.solicited_event = 1;
  1770. /* pad_count */
  1771. qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
  1772. /* P_key for QP1 is for all members */
  1773. qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
  1774. qp->qp1_hdr.bth.destination_qpn = IB_QP1;
  1775. qp->qp1_hdr.bth.ack_req = 0;
  1776. qp->send_psn++;
  1777. qp->send_psn &= BTH_PSN_MASK;
  1778. qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
  1779. /* DETH */
  1780. /* Use the priviledged Q_Key for QP1 */
  1781. qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
  1782. qp->qp1_hdr.deth.source_qpn = IB_QP1;
  1783. /* Pack the QP1 to the transmit buffer */
  1784. buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
  1785. if (buf) {
  1786. ib_ud_header_pack(&qp->qp1_hdr, buf);
  1787. for (i = wqe->num_sge; i; i--) {
  1788. wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
  1789. wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
  1790. wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
  1791. }
  1792. /*
  1793. * Max Header buf size for IPV6 RoCE V2 is 86,
  1794. * which is same as the QP1 SQ header buffer.
  1795. * Header buf size for IPV4 RoCE V2 can be 66.
  1796. * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
  1797. * Subtract 20 bytes from QP1 SQ header buf size
  1798. */
  1799. if (is_udp && ip_version == 4)
  1800. sge.size -= 20;
  1801. /*
  1802. * Max Header buf size for RoCE V1 is 78.
  1803. * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
  1804. * Subtract 8 bytes from QP1 SQ header buf size
  1805. */
  1806. if (!is_udp)
  1807. sge.size -= 8;
  1808. /* Subtract 4 bytes for non vlan packets */
  1809. if (!is_vlan)
  1810. sge.size -= 4;
  1811. wqe->sg_list[0].addr = sge.addr;
  1812. wqe->sg_list[0].lkey = sge.lkey;
  1813. wqe->sg_list[0].size = sge.size;
  1814. wqe->num_sge++;
  1815. } else {
  1816. dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
  1817. rc = -ENOMEM;
  1818. }
  1819. return rc;
  1820. }
  1821. /* For the MAD layer, it only provides the recv SGE the size of
  1822. * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
  1823. * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
  1824. * receive packet (334 bytes) with no VLAN and then copy the GRH
  1825. * and the MAD datagram out to the provided SGE.
  1826. */
  1827. static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
  1828. const struct ib_recv_wr *wr,
  1829. struct bnxt_qplib_swqe *wqe,
  1830. int payload_size)
  1831. {
  1832. struct bnxt_qplib_sge ref, sge;
  1833. u32 rq_prod_index;
  1834. struct bnxt_re_sqp_entries *sqp_entry;
  1835. rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
  1836. if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
  1837. return -ENOMEM;
  1838. /* Create 1 SGE to receive the entire
  1839. * ethernet packet
  1840. */
  1841. /* Save the reference from ULP */
  1842. ref.addr = wqe->sg_list[0].addr;
  1843. ref.lkey = wqe->sg_list[0].lkey;
  1844. ref.size = wqe->sg_list[0].size;
  1845. sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
  1846. /* SGE 1 */
  1847. wqe->sg_list[0].addr = sge.addr;
  1848. wqe->sg_list[0].lkey = sge.lkey;
  1849. wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
  1850. sge.size -= wqe->sg_list[0].size;
  1851. sqp_entry->sge.addr = ref.addr;
  1852. sqp_entry->sge.lkey = ref.lkey;
  1853. sqp_entry->sge.size = ref.size;
  1854. /* Store the wrid for reporting completion */
  1855. sqp_entry->wrid = wqe->wr_id;
  1856. /* change the wqe->wrid to table index */
  1857. wqe->wr_id = rq_prod_index;
  1858. return 0;
  1859. }
  1860. static int is_ud_qp(struct bnxt_re_qp *qp)
  1861. {
  1862. return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
  1863. }
  1864. static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
  1865. const struct ib_send_wr *wr,
  1866. struct bnxt_qplib_swqe *wqe)
  1867. {
  1868. struct bnxt_re_ah *ah = NULL;
  1869. if (is_ud_qp(qp)) {
  1870. ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
  1871. wqe->send.q_key = ud_wr(wr)->remote_qkey;
  1872. wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
  1873. wqe->send.avid = ah->qplib_ah.id;
  1874. }
  1875. switch (wr->opcode) {
  1876. case IB_WR_SEND:
  1877. wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
  1878. break;
  1879. case IB_WR_SEND_WITH_IMM:
  1880. wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
  1881. wqe->send.imm_data = wr->ex.imm_data;
  1882. break;
  1883. case IB_WR_SEND_WITH_INV:
  1884. wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
  1885. wqe->send.inv_key = wr->ex.invalidate_rkey;
  1886. break;
  1887. default:
  1888. return -EINVAL;
  1889. }
  1890. if (wr->send_flags & IB_SEND_SIGNALED)
  1891. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1892. if (wr->send_flags & IB_SEND_FENCE)
  1893. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1894. if (wr->send_flags & IB_SEND_SOLICITED)
  1895. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1896. if (wr->send_flags & IB_SEND_INLINE)
  1897. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
  1898. return 0;
  1899. }
  1900. static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
  1901. struct bnxt_qplib_swqe *wqe)
  1902. {
  1903. switch (wr->opcode) {
  1904. case IB_WR_RDMA_WRITE:
  1905. wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
  1906. break;
  1907. case IB_WR_RDMA_WRITE_WITH_IMM:
  1908. wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
  1909. wqe->rdma.imm_data = wr->ex.imm_data;
  1910. break;
  1911. case IB_WR_RDMA_READ:
  1912. wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
  1913. wqe->rdma.inv_key = wr->ex.invalidate_rkey;
  1914. break;
  1915. default:
  1916. return -EINVAL;
  1917. }
  1918. wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
  1919. wqe->rdma.r_key = rdma_wr(wr)->rkey;
  1920. if (wr->send_flags & IB_SEND_SIGNALED)
  1921. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1922. if (wr->send_flags & IB_SEND_FENCE)
  1923. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1924. if (wr->send_flags & IB_SEND_SOLICITED)
  1925. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1926. if (wr->send_flags & IB_SEND_INLINE)
  1927. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
  1928. return 0;
  1929. }
  1930. static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
  1931. struct bnxt_qplib_swqe *wqe)
  1932. {
  1933. switch (wr->opcode) {
  1934. case IB_WR_ATOMIC_CMP_AND_SWP:
  1935. wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
  1936. wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
  1937. wqe->atomic.swap_data = atomic_wr(wr)->swap;
  1938. break;
  1939. case IB_WR_ATOMIC_FETCH_AND_ADD:
  1940. wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
  1941. wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
  1942. break;
  1943. default:
  1944. return -EINVAL;
  1945. }
  1946. wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
  1947. wqe->atomic.r_key = atomic_wr(wr)->rkey;
  1948. if (wr->send_flags & IB_SEND_SIGNALED)
  1949. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1950. if (wr->send_flags & IB_SEND_FENCE)
  1951. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1952. if (wr->send_flags & IB_SEND_SOLICITED)
  1953. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1954. return 0;
  1955. }
  1956. static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
  1957. struct bnxt_qplib_swqe *wqe)
  1958. {
  1959. wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
  1960. wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
  1961. /* Need unconditional fence for local invalidate
  1962. * opcode to work as expected.
  1963. */
  1964. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1965. if (wr->send_flags & IB_SEND_SIGNALED)
  1966. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1967. if (wr->send_flags & IB_SEND_SOLICITED)
  1968. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
  1969. return 0;
  1970. }
  1971. static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
  1972. struct bnxt_qplib_swqe *wqe)
  1973. {
  1974. struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
  1975. struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
  1976. int access = wr->access;
  1977. wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
  1978. wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
  1979. wqe->frmr.page_list = mr->pages;
  1980. wqe->frmr.page_list_len = mr->npages;
  1981. wqe->frmr.levels = qplib_frpl->hwq.level + 1;
  1982. wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
  1983. /* Need unconditional fence for reg_mr
  1984. * opcode to function as expected.
  1985. */
  1986. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
  1987. if (wr->wr.send_flags & IB_SEND_SIGNALED)
  1988. wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
  1989. if (access & IB_ACCESS_LOCAL_WRITE)
  1990. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
  1991. if (access & IB_ACCESS_REMOTE_READ)
  1992. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
  1993. if (access & IB_ACCESS_REMOTE_WRITE)
  1994. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
  1995. if (access & IB_ACCESS_REMOTE_ATOMIC)
  1996. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
  1997. if (access & IB_ACCESS_MW_BIND)
  1998. wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
  1999. wqe->frmr.l_key = wr->key;
  2000. wqe->frmr.length = wr->mr->length;
  2001. wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
  2002. wqe->frmr.va = wr->mr->iova;
  2003. return 0;
  2004. }
  2005. static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
  2006. const struct ib_send_wr *wr,
  2007. struct bnxt_qplib_swqe *wqe)
  2008. {
  2009. /* Copy the inline data to the data field */
  2010. u8 *in_data;
  2011. u32 i, sge_len;
  2012. void *sge_addr;
  2013. in_data = wqe->inline_data;
  2014. for (i = 0; i < wr->num_sge; i++) {
  2015. sge_addr = (void *)(unsigned long)
  2016. wr->sg_list[i].addr;
  2017. sge_len = wr->sg_list[i].length;
  2018. if ((sge_len + wqe->inline_len) >
  2019. BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
  2020. dev_err(rdev_to_dev(rdev),
  2021. "Inline data size requested > supported value");
  2022. return -EINVAL;
  2023. }
  2024. sge_len = wr->sg_list[i].length;
  2025. memcpy(in_data, sge_addr, sge_len);
  2026. in_data += wr->sg_list[i].length;
  2027. wqe->inline_len += wr->sg_list[i].length;
  2028. }
  2029. return wqe->inline_len;
  2030. }
  2031. static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
  2032. const struct ib_send_wr *wr,
  2033. struct bnxt_qplib_swqe *wqe)
  2034. {
  2035. int payload_sz = 0;
  2036. if (wr->send_flags & IB_SEND_INLINE)
  2037. payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
  2038. else
  2039. payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
  2040. wqe->num_sge);
  2041. return payload_sz;
  2042. }
  2043. static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
  2044. {
  2045. if ((qp->ib_qp.qp_type == IB_QPT_UD ||
  2046. qp->ib_qp.qp_type == IB_QPT_GSI ||
  2047. qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
  2048. qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
  2049. int qp_attr_mask;
  2050. struct ib_qp_attr qp_attr;
  2051. qp_attr_mask = IB_QP_STATE;
  2052. qp_attr.qp_state = IB_QPS_RTS;
  2053. bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
  2054. qp->qplib_qp.wqe_cnt = 0;
  2055. }
  2056. }
  2057. static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
  2058. struct bnxt_re_qp *qp,
  2059. const struct ib_send_wr *wr)
  2060. {
  2061. struct bnxt_qplib_swqe wqe;
  2062. int rc = 0, payload_sz = 0;
  2063. unsigned long flags;
  2064. spin_lock_irqsave(&qp->sq_lock, flags);
  2065. memset(&wqe, 0, sizeof(wqe));
  2066. while (wr) {
  2067. /* House keeping */
  2068. memset(&wqe, 0, sizeof(wqe));
  2069. /* Common */
  2070. wqe.num_sge = wr->num_sge;
  2071. if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
  2072. dev_err(rdev_to_dev(rdev),
  2073. "Limit exceeded for Send SGEs");
  2074. rc = -EINVAL;
  2075. goto bad;
  2076. }
  2077. payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
  2078. if (payload_sz < 0) {
  2079. rc = -EINVAL;
  2080. goto bad;
  2081. }
  2082. wqe.wr_id = wr->wr_id;
  2083. wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
  2084. rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
  2085. if (!rc)
  2086. rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
  2087. bad:
  2088. if (rc) {
  2089. dev_err(rdev_to_dev(rdev),
  2090. "Post send failed opcode = %#x rc = %d",
  2091. wr->opcode, rc);
  2092. break;
  2093. }
  2094. wr = wr->next;
  2095. }
  2096. bnxt_qplib_post_send_db(&qp->qplib_qp);
  2097. bnxt_ud_qp_hw_stall_workaround(qp);
  2098. spin_unlock_irqrestore(&qp->sq_lock, flags);
  2099. return rc;
  2100. }
  2101. int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
  2102. const struct ib_send_wr **bad_wr)
  2103. {
  2104. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  2105. struct bnxt_qplib_swqe wqe;
  2106. int rc = 0, payload_sz = 0;
  2107. unsigned long flags;
  2108. spin_lock_irqsave(&qp->sq_lock, flags);
  2109. while (wr) {
  2110. /* House keeping */
  2111. memset(&wqe, 0, sizeof(wqe));
  2112. /* Common */
  2113. wqe.num_sge = wr->num_sge;
  2114. if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
  2115. dev_err(rdev_to_dev(qp->rdev),
  2116. "Limit exceeded for Send SGEs");
  2117. rc = -EINVAL;
  2118. goto bad;
  2119. }
  2120. payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
  2121. if (payload_sz < 0) {
  2122. rc = -EINVAL;
  2123. goto bad;
  2124. }
  2125. wqe.wr_id = wr->wr_id;
  2126. switch (wr->opcode) {
  2127. case IB_WR_SEND:
  2128. case IB_WR_SEND_WITH_IMM:
  2129. if (ib_qp->qp_type == IB_QPT_GSI) {
  2130. rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
  2131. payload_sz);
  2132. if (rc)
  2133. goto bad;
  2134. wqe.rawqp1.lflags |=
  2135. SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
  2136. }
  2137. switch (wr->send_flags) {
  2138. case IB_SEND_IP_CSUM:
  2139. wqe.rawqp1.lflags |=
  2140. SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
  2141. break;
  2142. default:
  2143. break;
  2144. }
  2145. /* fall through */
  2146. case IB_WR_SEND_WITH_INV:
  2147. rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
  2148. break;
  2149. case IB_WR_RDMA_WRITE:
  2150. case IB_WR_RDMA_WRITE_WITH_IMM:
  2151. case IB_WR_RDMA_READ:
  2152. rc = bnxt_re_build_rdma_wqe(wr, &wqe);
  2153. break;
  2154. case IB_WR_ATOMIC_CMP_AND_SWP:
  2155. case IB_WR_ATOMIC_FETCH_AND_ADD:
  2156. rc = bnxt_re_build_atomic_wqe(wr, &wqe);
  2157. break;
  2158. case IB_WR_RDMA_READ_WITH_INV:
  2159. dev_err(rdev_to_dev(qp->rdev),
  2160. "RDMA Read with Invalidate is not supported");
  2161. rc = -EINVAL;
  2162. goto bad;
  2163. case IB_WR_LOCAL_INV:
  2164. rc = bnxt_re_build_inv_wqe(wr, &wqe);
  2165. break;
  2166. case IB_WR_REG_MR:
  2167. rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
  2168. break;
  2169. default:
  2170. /* Unsupported WRs */
  2171. dev_err(rdev_to_dev(qp->rdev),
  2172. "WR (%#x) is not supported", wr->opcode);
  2173. rc = -EINVAL;
  2174. goto bad;
  2175. }
  2176. if (!rc)
  2177. rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
  2178. bad:
  2179. if (rc) {
  2180. dev_err(rdev_to_dev(qp->rdev),
  2181. "post_send failed op:%#x qps = %#x rc = %d\n",
  2182. wr->opcode, qp->qplib_qp.state, rc);
  2183. *bad_wr = wr;
  2184. break;
  2185. }
  2186. wr = wr->next;
  2187. }
  2188. bnxt_qplib_post_send_db(&qp->qplib_qp);
  2189. bnxt_ud_qp_hw_stall_workaround(qp);
  2190. spin_unlock_irqrestore(&qp->sq_lock, flags);
  2191. return rc;
  2192. }
  2193. static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
  2194. struct bnxt_re_qp *qp,
  2195. const struct ib_recv_wr *wr)
  2196. {
  2197. struct bnxt_qplib_swqe wqe;
  2198. int rc = 0;
  2199. memset(&wqe, 0, sizeof(wqe));
  2200. while (wr) {
  2201. /* House keeping */
  2202. memset(&wqe, 0, sizeof(wqe));
  2203. /* Common */
  2204. wqe.num_sge = wr->num_sge;
  2205. if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
  2206. dev_err(rdev_to_dev(rdev),
  2207. "Limit exceeded for Receive SGEs");
  2208. rc = -EINVAL;
  2209. break;
  2210. }
  2211. bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
  2212. wqe.wr_id = wr->wr_id;
  2213. wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
  2214. rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
  2215. if (rc)
  2216. break;
  2217. wr = wr->next;
  2218. }
  2219. if (!rc)
  2220. bnxt_qplib_post_recv_db(&qp->qplib_qp);
  2221. return rc;
  2222. }
  2223. int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
  2224. const struct ib_recv_wr **bad_wr)
  2225. {
  2226. struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
  2227. struct bnxt_qplib_swqe wqe;
  2228. int rc = 0, payload_sz = 0;
  2229. unsigned long flags;
  2230. u32 count = 0;
  2231. spin_lock_irqsave(&qp->rq_lock, flags);
  2232. while (wr) {
  2233. /* House keeping */
  2234. memset(&wqe, 0, sizeof(wqe));
  2235. /* Common */
  2236. wqe.num_sge = wr->num_sge;
  2237. if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
  2238. dev_err(rdev_to_dev(qp->rdev),
  2239. "Limit exceeded for Receive SGEs");
  2240. rc = -EINVAL;
  2241. *bad_wr = wr;
  2242. break;
  2243. }
  2244. payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
  2245. wr->num_sge);
  2246. wqe.wr_id = wr->wr_id;
  2247. wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
  2248. if (ib_qp->qp_type == IB_QPT_GSI)
  2249. rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
  2250. payload_sz);
  2251. if (!rc)
  2252. rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
  2253. if (rc) {
  2254. *bad_wr = wr;
  2255. break;
  2256. }
  2257. /* Ring DB if the RQEs posted reaches a threshold value */
  2258. if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
  2259. bnxt_qplib_post_recv_db(&qp->qplib_qp);
  2260. count = 0;
  2261. }
  2262. wr = wr->next;
  2263. }
  2264. if (count)
  2265. bnxt_qplib_post_recv_db(&qp->qplib_qp);
  2266. spin_unlock_irqrestore(&qp->rq_lock, flags);
  2267. return rc;
  2268. }
  2269. /* Completion Queues */
  2270. int bnxt_re_destroy_cq(struct ib_cq *ib_cq)
  2271. {
  2272. int rc;
  2273. struct bnxt_re_cq *cq;
  2274. struct bnxt_qplib_nq *nq;
  2275. struct bnxt_re_dev *rdev;
  2276. cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
  2277. rdev = cq->rdev;
  2278. nq = cq->qplib_cq.nq;
  2279. rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
  2280. if (rc) {
  2281. dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
  2282. return rc;
  2283. }
  2284. if (!IS_ERR_OR_NULL(cq->umem))
  2285. ib_umem_release(cq->umem);
  2286. atomic_dec(&rdev->cq_count);
  2287. nq->budget--;
  2288. kfree(cq->cql);
  2289. kfree(cq);
  2290. return 0;
  2291. }
  2292. struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
  2293. const struct ib_cq_init_attr *attr,
  2294. struct ib_ucontext *context,
  2295. struct ib_udata *udata)
  2296. {
  2297. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  2298. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  2299. struct bnxt_re_cq *cq = NULL;
  2300. int rc, entries;
  2301. int cqe = attr->cqe;
  2302. struct bnxt_qplib_nq *nq = NULL;
  2303. unsigned int nq_alloc_cnt;
  2304. /* Validate CQ fields */
  2305. if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
  2306. dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
  2307. return ERR_PTR(-EINVAL);
  2308. }
  2309. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  2310. if (!cq)
  2311. return ERR_PTR(-ENOMEM);
  2312. cq->rdev = rdev;
  2313. cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
  2314. entries = roundup_pow_of_two(cqe + 1);
  2315. if (entries > dev_attr->max_cq_wqes + 1)
  2316. entries = dev_attr->max_cq_wqes + 1;
  2317. if (context) {
  2318. struct bnxt_re_cq_req req;
  2319. struct bnxt_re_ucontext *uctx = container_of
  2320. (context,
  2321. struct bnxt_re_ucontext,
  2322. ib_uctx);
  2323. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  2324. rc = -EFAULT;
  2325. goto fail;
  2326. }
  2327. cq->umem = ib_umem_get(context, req.cq_va,
  2328. entries * sizeof(struct cq_base),
  2329. IB_ACCESS_LOCAL_WRITE, 1);
  2330. if (IS_ERR(cq->umem)) {
  2331. rc = PTR_ERR(cq->umem);
  2332. goto fail;
  2333. }
  2334. cq->qplib_cq.sghead = cq->umem->sg_head.sgl;
  2335. cq->qplib_cq.nmap = cq->umem->nmap;
  2336. cq->qplib_cq.dpi = &uctx->dpi;
  2337. } else {
  2338. cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
  2339. cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
  2340. GFP_KERNEL);
  2341. if (!cq->cql) {
  2342. rc = -ENOMEM;
  2343. goto fail;
  2344. }
  2345. cq->qplib_cq.dpi = &rdev->dpi_privileged;
  2346. cq->qplib_cq.sghead = NULL;
  2347. cq->qplib_cq.nmap = 0;
  2348. }
  2349. /*
  2350. * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
  2351. * used for getting the NQ index.
  2352. */
  2353. nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
  2354. nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
  2355. cq->qplib_cq.max_wqe = entries;
  2356. cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
  2357. cq->qplib_cq.nq = nq;
  2358. rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
  2359. if (rc) {
  2360. dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
  2361. goto fail;
  2362. }
  2363. cq->ib_cq.cqe = entries;
  2364. cq->cq_period = cq->qplib_cq.period;
  2365. nq->budget++;
  2366. atomic_inc(&rdev->cq_count);
  2367. spin_lock_init(&cq->cq_lock);
  2368. if (context) {
  2369. struct bnxt_re_cq_resp resp;
  2370. resp.cqid = cq->qplib_cq.id;
  2371. resp.tail = cq->qplib_cq.hwq.cons;
  2372. resp.phase = cq->qplib_cq.period;
  2373. resp.rsvd = 0;
  2374. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  2375. if (rc) {
  2376. dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
  2377. bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
  2378. goto c2fail;
  2379. }
  2380. }
  2381. return &cq->ib_cq;
  2382. c2fail:
  2383. if (context)
  2384. ib_umem_release(cq->umem);
  2385. fail:
  2386. kfree(cq->cql);
  2387. kfree(cq);
  2388. return ERR_PTR(rc);
  2389. }
  2390. static u8 __req_to_ib_wc_status(u8 qstatus)
  2391. {
  2392. switch (qstatus) {
  2393. case CQ_REQ_STATUS_OK:
  2394. return IB_WC_SUCCESS;
  2395. case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
  2396. return IB_WC_BAD_RESP_ERR;
  2397. case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
  2398. return IB_WC_LOC_LEN_ERR;
  2399. case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
  2400. return IB_WC_LOC_QP_OP_ERR;
  2401. case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
  2402. return IB_WC_LOC_PROT_ERR;
  2403. case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
  2404. return IB_WC_GENERAL_ERR;
  2405. case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
  2406. return IB_WC_REM_INV_REQ_ERR;
  2407. case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
  2408. return IB_WC_REM_ACCESS_ERR;
  2409. case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
  2410. return IB_WC_REM_OP_ERR;
  2411. case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
  2412. return IB_WC_RNR_RETRY_EXC_ERR;
  2413. case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
  2414. return IB_WC_RETRY_EXC_ERR;
  2415. case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
  2416. return IB_WC_WR_FLUSH_ERR;
  2417. default:
  2418. return IB_WC_GENERAL_ERR;
  2419. }
  2420. return 0;
  2421. }
  2422. static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
  2423. {
  2424. switch (qstatus) {
  2425. case CQ_RES_RAWETH_QP1_STATUS_OK:
  2426. return IB_WC_SUCCESS;
  2427. case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
  2428. return IB_WC_LOC_ACCESS_ERR;
  2429. case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
  2430. return IB_WC_LOC_LEN_ERR;
  2431. case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
  2432. return IB_WC_LOC_PROT_ERR;
  2433. case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
  2434. return IB_WC_LOC_QP_OP_ERR;
  2435. case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
  2436. return IB_WC_GENERAL_ERR;
  2437. case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
  2438. return IB_WC_WR_FLUSH_ERR;
  2439. case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
  2440. return IB_WC_WR_FLUSH_ERR;
  2441. default:
  2442. return IB_WC_GENERAL_ERR;
  2443. }
  2444. }
  2445. static u8 __rc_to_ib_wc_status(u8 qstatus)
  2446. {
  2447. switch (qstatus) {
  2448. case CQ_RES_RC_STATUS_OK:
  2449. return IB_WC_SUCCESS;
  2450. case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
  2451. return IB_WC_LOC_ACCESS_ERR;
  2452. case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
  2453. return IB_WC_LOC_LEN_ERR;
  2454. case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
  2455. return IB_WC_LOC_PROT_ERR;
  2456. case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
  2457. return IB_WC_LOC_QP_OP_ERR;
  2458. case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
  2459. return IB_WC_GENERAL_ERR;
  2460. case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
  2461. return IB_WC_REM_INV_REQ_ERR;
  2462. case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
  2463. return IB_WC_WR_FLUSH_ERR;
  2464. case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
  2465. return IB_WC_WR_FLUSH_ERR;
  2466. default:
  2467. return IB_WC_GENERAL_ERR;
  2468. }
  2469. }
  2470. static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
  2471. {
  2472. switch (cqe->type) {
  2473. case BNXT_QPLIB_SWQE_TYPE_SEND:
  2474. wc->opcode = IB_WC_SEND;
  2475. break;
  2476. case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
  2477. wc->opcode = IB_WC_SEND;
  2478. wc->wc_flags |= IB_WC_WITH_IMM;
  2479. break;
  2480. case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
  2481. wc->opcode = IB_WC_SEND;
  2482. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2483. break;
  2484. case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
  2485. wc->opcode = IB_WC_RDMA_WRITE;
  2486. break;
  2487. case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
  2488. wc->opcode = IB_WC_RDMA_WRITE;
  2489. wc->wc_flags |= IB_WC_WITH_IMM;
  2490. break;
  2491. case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
  2492. wc->opcode = IB_WC_RDMA_READ;
  2493. break;
  2494. case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
  2495. wc->opcode = IB_WC_COMP_SWAP;
  2496. break;
  2497. case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
  2498. wc->opcode = IB_WC_FETCH_ADD;
  2499. break;
  2500. case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
  2501. wc->opcode = IB_WC_LOCAL_INV;
  2502. break;
  2503. case BNXT_QPLIB_SWQE_TYPE_REG_MR:
  2504. wc->opcode = IB_WC_REG_MR;
  2505. break;
  2506. default:
  2507. wc->opcode = IB_WC_SEND;
  2508. break;
  2509. }
  2510. wc->status = __req_to_ib_wc_status(cqe->status);
  2511. }
  2512. static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
  2513. u16 raweth_qp1_flags2)
  2514. {
  2515. bool is_ipv6 = false, is_ipv4 = false;
  2516. /* raweth_qp1_flags Bit 9-6 indicates itype */
  2517. if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
  2518. != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
  2519. return -1;
  2520. if (raweth_qp1_flags2 &
  2521. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
  2522. raweth_qp1_flags2 &
  2523. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
  2524. /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
  2525. (raweth_qp1_flags2 &
  2526. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
  2527. (is_ipv6 = true) : (is_ipv4 = true);
  2528. return ((is_ipv6) ?
  2529. BNXT_RE_ROCEV2_IPV6_PACKET :
  2530. BNXT_RE_ROCEV2_IPV4_PACKET);
  2531. } else {
  2532. return BNXT_RE_ROCE_V1_PACKET;
  2533. }
  2534. }
  2535. static int bnxt_re_to_ib_nw_type(int nw_type)
  2536. {
  2537. u8 nw_hdr_type = 0xFF;
  2538. switch (nw_type) {
  2539. case BNXT_RE_ROCE_V1_PACKET:
  2540. nw_hdr_type = RDMA_NETWORK_ROCE_V1;
  2541. break;
  2542. case BNXT_RE_ROCEV2_IPV4_PACKET:
  2543. nw_hdr_type = RDMA_NETWORK_IPV4;
  2544. break;
  2545. case BNXT_RE_ROCEV2_IPV6_PACKET:
  2546. nw_hdr_type = RDMA_NETWORK_IPV6;
  2547. break;
  2548. }
  2549. return nw_hdr_type;
  2550. }
  2551. static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
  2552. void *rq_hdr_buf)
  2553. {
  2554. u8 *tmp_buf = NULL;
  2555. struct ethhdr *eth_hdr;
  2556. u16 eth_type;
  2557. bool rc = false;
  2558. tmp_buf = (u8 *)rq_hdr_buf;
  2559. /*
  2560. * If dest mac is not same as I/F mac, this could be a
  2561. * loopback address or multicast address, check whether
  2562. * it is a loopback packet
  2563. */
  2564. if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
  2565. tmp_buf += 4;
  2566. /* Check the ether type */
  2567. eth_hdr = (struct ethhdr *)tmp_buf;
  2568. eth_type = ntohs(eth_hdr->h_proto);
  2569. switch (eth_type) {
  2570. case ETH_P_IBOE:
  2571. rc = true;
  2572. break;
  2573. case ETH_P_IP:
  2574. case ETH_P_IPV6: {
  2575. u32 len;
  2576. struct udphdr *udp_hdr;
  2577. len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
  2578. sizeof(struct ipv6hdr));
  2579. tmp_buf += sizeof(struct ethhdr) + len;
  2580. udp_hdr = (struct udphdr *)tmp_buf;
  2581. if (ntohs(udp_hdr->dest) ==
  2582. ROCE_V2_UDP_DPORT)
  2583. rc = true;
  2584. break;
  2585. }
  2586. default:
  2587. break;
  2588. }
  2589. }
  2590. return rc;
  2591. }
  2592. static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
  2593. struct bnxt_qplib_cqe *cqe)
  2594. {
  2595. struct bnxt_re_dev *rdev = qp1_qp->rdev;
  2596. struct bnxt_re_sqp_entries *sqp_entry = NULL;
  2597. struct bnxt_re_qp *qp = rdev->qp1_sqp;
  2598. struct ib_send_wr *swr;
  2599. struct ib_ud_wr udwr;
  2600. struct ib_recv_wr rwr;
  2601. int pkt_type = 0;
  2602. u32 tbl_idx;
  2603. void *rq_hdr_buf;
  2604. dma_addr_t rq_hdr_buf_map;
  2605. dma_addr_t shrq_hdr_buf_map;
  2606. u32 offset = 0;
  2607. u32 skip_bytes = 0;
  2608. struct ib_sge s_sge[2];
  2609. struct ib_sge r_sge[2];
  2610. int rc;
  2611. memset(&udwr, 0, sizeof(udwr));
  2612. memset(&rwr, 0, sizeof(rwr));
  2613. memset(&s_sge, 0, sizeof(s_sge));
  2614. memset(&r_sge, 0, sizeof(r_sge));
  2615. swr = &udwr.wr;
  2616. tbl_idx = cqe->wr_id;
  2617. rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
  2618. (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
  2619. rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
  2620. tbl_idx);
  2621. /* Shadow QP header buffer */
  2622. shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
  2623. tbl_idx);
  2624. sqp_entry = &rdev->sqp_tbl[tbl_idx];
  2625. /* Store this cqe */
  2626. memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
  2627. sqp_entry->qp1_qp = qp1_qp;
  2628. /* Find packet type from the cqe */
  2629. pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
  2630. cqe->raweth_qp1_flags2);
  2631. if (pkt_type < 0) {
  2632. dev_err(rdev_to_dev(rdev), "Invalid packet\n");
  2633. return -EINVAL;
  2634. }
  2635. /* Adjust the offset for the user buffer and post in the rq */
  2636. if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
  2637. offset = 20;
  2638. /*
  2639. * QP1 loopback packet has 4 bytes of internal header before
  2640. * ether header. Skip these four bytes.
  2641. */
  2642. if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
  2643. skip_bytes = 4;
  2644. /* First send SGE . Skip the ether header*/
  2645. s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
  2646. + skip_bytes;
  2647. s_sge[0].lkey = 0xFFFFFFFF;
  2648. s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
  2649. BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
  2650. /* Second Send SGE */
  2651. s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
  2652. BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
  2653. if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
  2654. s_sge[1].addr += 8;
  2655. s_sge[1].lkey = 0xFFFFFFFF;
  2656. s_sge[1].length = 256;
  2657. /* First recv SGE */
  2658. r_sge[0].addr = shrq_hdr_buf_map;
  2659. r_sge[0].lkey = 0xFFFFFFFF;
  2660. r_sge[0].length = 40;
  2661. r_sge[1].addr = sqp_entry->sge.addr + offset;
  2662. r_sge[1].lkey = sqp_entry->sge.lkey;
  2663. r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
  2664. /* Create receive work request */
  2665. rwr.num_sge = 2;
  2666. rwr.sg_list = r_sge;
  2667. rwr.wr_id = tbl_idx;
  2668. rwr.next = NULL;
  2669. rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
  2670. if (rc) {
  2671. dev_err(rdev_to_dev(rdev),
  2672. "Failed to post Rx buffers to shadow QP");
  2673. return -ENOMEM;
  2674. }
  2675. swr->num_sge = 2;
  2676. swr->sg_list = s_sge;
  2677. swr->wr_id = tbl_idx;
  2678. swr->opcode = IB_WR_SEND;
  2679. swr->next = NULL;
  2680. udwr.ah = &rdev->sqp_ah->ib_ah;
  2681. udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
  2682. udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
  2683. /* post data received in the send queue */
  2684. rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
  2685. return 0;
  2686. }
  2687. static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
  2688. struct bnxt_qplib_cqe *cqe)
  2689. {
  2690. wc->opcode = IB_WC_RECV;
  2691. wc->status = __rawqp1_to_ib_wc_status(cqe->status);
  2692. wc->wc_flags |= IB_WC_GRH;
  2693. }
  2694. static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
  2695. u16 vlan_id)
  2696. {
  2697. /*
  2698. * Check if the vlan is configured in the host. If not configured, it
  2699. * can be a transparent VLAN. So dont report the vlan id.
  2700. */
  2701. if (!__vlan_find_dev_deep_rcu(rdev->netdev,
  2702. htons(ETH_P_8021Q), vlan_id))
  2703. return false;
  2704. return true;
  2705. }
  2706. static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
  2707. u16 *vid, u8 *sl)
  2708. {
  2709. bool ret = false;
  2710. u32 metadata;
  2711. u16 tpid;
  2712. metadata = orig_cqe->raweth_qp1_metadata;
  2713. if (orig_cqe->raweth_qp1_flags2 &
  2714. CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
  2715. tpid = ((metadata &
  2716. CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
  2717. CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
  2718. if (tpid == ETH_P_8021Q) {
  2719. *vid = metadata &
  2720. CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
  2721. *sl = (metadata &
  2722. CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
  2723. CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
  2724. ret = true;
  2725. }
  2726. }
  2727. return ret;
  2728. }
  2729. static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
  2730. struct bnxt_qplib_cqe *cqe)
  2731. {
  2732. wc->opcode = IB_WC_RECV;
  2733. wc->status = __rc_to_ib_wc_status(cqe->status);
  2734. if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
  2735. wc->wc_flags |= IB_WC_WITH_IMM;
  2736. if (cqe->flags & CQ_RES_RC_FLAGS_INV)
  2737. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2738. if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
  2739. (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
  2740. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2741. }
  2742. static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
  2743. struct ib_wc *wc,
  2744. struct bnxt_qplib_cqe *cqe)
  2745. {
  2746. struct bnxt_re_dev *rdev = qp->rdev;
  2747. struct bnxt_re_qp *qp1_qp = NULL;
  2748. struct bnxt_qplib_cqe *orig_cqe = NULL;
  2749. struct bnxt_re_sqp_entries *sqp_entry = NULL;
  2750. int nw_type;
  2751. u32 tbl_idx;
  2752. u16 vlan_id;
  2753. u8 sl;
  2754. tbl_idx = cqe->wr_id;
  2755. sqp_entry = &rdev->sqp_tbl[tbl_idx];
  2756. qp1_qp = sqp_entry->qp1_qp;
  2757. orig_cqe = &sqp_entry->cqe;
  2758. wc->wr_id = sqp_entry->wrid;
  2759. wc->byte_len = orig_cqe->length;
  2760. wc->qp = &qp1_qp->ib_qp;
  2761. wc->ex.imm_data = orig_cqe->immdata;
  2762. wc->src_qp = orig_cqe->src_qp;
  2763. memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
  2764. if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
  2765. if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
  2766. wc->vlan_id = vlan_id;
  2767. wc->sl = sl;
  2768. wc->wc_flags |= IB_WC_WITH_VLAN;
  2769. }
  2770. }
  2771. wc->port_num = 1;
  2772. wc->vendor_err = orig_cqe->status;
  2773. wc->opcode = IB_WC_RECV;
  2774. wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
  2775. wc->wc_flags |= IB_WC_GRH;
  2776. nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
  2777. orig_cqe->raweth_qp1_flags2);
  2778. if (nw_type >= 0) {
  2779. wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
  2780. wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
  2781. }
  2782. }
  2783. static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
  2784. struct bnxt_qplib_cqe *cqe)
  2785. {
  2786. wc->opcode = IB_WC_RECV;
  2787. wc->status = __rc_to_ib_wc_status(cqe->status);
  2788. if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
  2789. wc->wc_flags |= IB_WC_WITH_IMM;
  2790. if (cqe->flags & CQ_RES_RC_FLAGS_INV)
  2791. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2792. if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
  2793. (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
  2794. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2795. }
  2796. static int send_phantom_wqe(struct bnxt_re_qp *qp)
  2797. {
  2798. struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
  2799. unsigned long flags;
  2800. int rc = 0;
  2801. spin_lock_irqsave(&qp->sq_lock, flags);
  2802. rc = bnxt_re_bind_fence_mw(lib_qp);
  2803. if (!rc) {
  2804. lib_qp->sq.phantom_wqe_cnt++;
  2805. dev_dbg(&lib_qp->sq.hwq.pdev->dev,
  2806. "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
  2807. lib_qp->id, lib_qp->sq.hwq.prod,
  2808. HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
  2809. lib_qp->sq.phantom_wqe_cnt);
  2810. }
  2811. spin_unlock_irqrestore(&qp->sq_lock, flags);
  2812. return rc;
  2813. }
  2814. int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
  2815. {
  2816. struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
  2817. struct bnxt_re_qp *qp;
  2818. struct bnxt_qplib_cqe *cqe;
  2819. int i, ncqe, budget;
  2820. struct bnxt_qplib_q *sq;
  2821. struct bnxt_qplib_qp *lib_qp;
  2822. u32 tbl_idx;
  2823. struct bnxt_re_sqp_entries *sqp_entry = NULL;
  2824. unsigned long flags;
  2825. spin_lock_irqsave(&cq->cq_lock, flags);
  2826. budget = min_t(u32, num_entries, cq->max_cql);
  2827. num_entries = budget;
  2828. if (!cq->cql) {
  2829. dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
  2830. goto exit;
  2831. }
  2832. cqe = &cq->cql[0];
  2833. while (budget) {
  2834. lib_qp = NULL;
  2835. ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
  2836. if (lib_qp) {
  2837. sq = &lib_qp->sq;
  2838. if (sq->send_phantom) {
  2839. qp = container_of(lib_qp,
  2840. struct bnxt_re_qp, qplib_qp);
  2841. if (send_phantom_wqe(qp) == -ENOMEM)
  2842. dev_err(rdev_to_dev(cq->rdev),
  2843. "Phantom failed! Scheduled to send again\n");
  2844. else
  2845. sq->send_phantom = false;
  2846. }
  2847. }
  2848. if (ncqe < budget)
  2849. ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
  2850. cqe + ncqe,
  2851. budget - ncqe);
  2852. if (!ncqe)
  2853. break;
  2854. for (i = 0; i < ncqe; i++, cqe++) {
  2855. /* Transcribe each qplib_wqe back to ib_wc */
  2856. memset(wc, 0, sizeof(*wc));
  2857. wc->wr_id = cqe->wr_id;
  2858. wc->byte_len = cqe->length;
  2859. qp = container_of
  2860. ((struct bnxt_qplib_qp *)
  2861. (unsigned long)(cqe->qp_handle),
  2862. struct bnxt_re_qp, qplib_qp);
  2863. if (!qp) {
  2864. dev_err(rdev_to_dev(cq->rdev),
  2865. "POLL CQ : bad QP handle");
  2866. continue;
  2867. }
  2868. wc->qp = &qp->ib_qp;
  2869. wc->ex.imm_data = cqe->immdata;
  2870. wc->src_qp = cqe->src_qp;
  2871. memcpy(wc->smac, cqe->smac, ETH_ALEN);
  2872. wc->port_num = 1;
  2873. wc->vendor_err = cqe->status;
  2874. switch (cqe->opcode) {
  2875. case CQ_BASE_CQE_TYPE_REQ:
  2876. if (qp->qplib_qp.id ==
  2877. qp->rdev->qp1_sqp->qplib_qp.id) {
  2878. /* Handle this completion with
  2879. * the stored completion
  2880. */
  2881. memset(wc, 0, sizeof(*wc));
  2882. continue;
  2883. }
  2884. bnxt_re_process_req_wc(wc, cqe);
  2885. break;
  2886. case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
  2887. if (!cqe->status) {
  2888. int rc = 0;
  2889. rc = bnxt_re_process_raw_qp_pkt_rx
  2890. (qp, cqe);
  2891. if (!rc) {
  2892. memset(wc, 0, sizeof(*wc));
  2893. continue;
  2894. }
  2895. cqe->status = -1;
  2896. }
  2897. /* Errors need not be looped back.
  2898. * But change the wr_id to the one
  2899. * stored in the table
  2900. */
  2901. tbl_idx = cqe->wr_id;
  2902. sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
  2903. wc->wr_id = sqp_entry->wrid;
  2904. bnxt_re_process_res_rawqp1_wc(wc, cqe);
  2905. break;
  2906. case CQ_BASE_CQE_TYPE_RES_RC:
  2907. bnxt_re_process_res_rc_wc(wc, cqe);
  2908. break;
  2909. case CQ_BASE_CQE_TYPE_RES_UD:
  2910. if (qp->qplib_qp.id ==
  2911. qp->rdev->qp1_sqp->qplib_qp.id) {
  2912. /* Handle this completion with
  2913. * the stored completion
  2914. */
  2915. if (cqe->status) {
  2916. continue;
  2917. } else {
  2918. bnxt_re_process_res_shadow_qp_wc
  2919. (qp, wc, cqe);
  2920. break;
  2921. }
  2922. }
  2923. bnxt_re_process_res_ud_wc(wc, cqe);
  2924. break;
  2925. default:
  2926. dev_err(rdev_to_dev(cq->rdev),
  2927. "POLL CQ : type 0x%x not handled",
  2928. cqe->opcode);
  2929. continue;
  2930. }
  2931. wc++;
  2932. budget--;
  2933. }
  2934. }
  2935. exit:
  2936. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2937. return num_entries - budget;
  2938. }
  2939. int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
  2940. enum ib_cq_notify_flags ib_cqn_flags)
  2941. {
  2942. struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
  2943. int type = 0, rc = 0;
  2944. unsigned long flags;
  2945. spin_lock_irqsave(&cq->cq_lock, flags);
  2946. /* Trigger on the very next completion */
  2947. if (ib_cqn_flags & IB_CQ_NEXT_COMP)
  2948. type = DBR_DBR_TYPE_CQ_ARMALL;
  2949. /* Trigger on the next solicited completion */
  2950. else if (ib_cqn_flags & IB_CQ_SOLICITED)
  2951. type = DBR_DBR_TYPE_CQ_ARMSE;
  2952. /* Poll to see if there are missed events */
  2953. if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
  2954. !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
  2955. rc = 1;
  2956. goto exit;
  2957. }
  2958. bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
  2959. exit:
  2960. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2961. return rc;
  2962. }
  2963. /* Memory Regions */
  2964. struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
  2965. {
  2966. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  2967. struct bnxt_re_dev *rdev = pd->rdev;
  2968. struct bnxt_re_mr *mr;
  2969. u64 pbl = 0;
  2970. int rc;
  2971. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2972. if (!mr)
  2973. return ERR_PTR(-ENOMEM);
  2974. mr->rdev = rdev;
  2975. mr->qplib_mr.pd = &pd->qplib_pd;
  2976. mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
  2977. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
  2978. /* Allocate and register 0 as the address */
  2979. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2980. if (rc)
  2981. goto fail;
  2982. mr->qplib_mr.hwq.level = PBL_LVL_MAX;
  2983. mr->qplib_mr.total_size = -1; /* Infinte length */
  2984. rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false,
  2985. PAGE_SIZE);
  2986. if (rc)
  2987. goto fail_mr;
  2988. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  2989. if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
  2990. IB_ACCESS_REMOTE_ATOMIC))
  2991. mr->ib_mr.rkey = mr->ib_mr.lkey;
  2992. atomic_inc(&rdev->mr_count);
  2993. return &mr->ib_mr;
  2994. fail_mr:
  2995. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  2996. fail:
  2997. kfree(mr);
  2998. return ERR_PTR(rc);
  2999. }
  3000. int bnxt_re_dereg_mr(struct ib_mr *ib_mr)
  3001. {
  3002. struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
  3003. struct bnxt_re_dev *rdev = mr->rdev;
  3004. int rc;
  3005. rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  3006. if (rc) {
  3007. dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
  3008. return rc;
  3009. }
  3010. if (mr->pages) {
  3011. rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
  3012. &mr->qplib_frpl);
  3013. kfree(mr->pages);
  3014. mr->npages = 0;
  3015. mr->pages = NULL;
  3016. }
  3017. if (!IS_ERR_OR_NULL(mr->ib_umem))
  3018. ib_umem_release(mr->ib_umem);
  3019. kfree(mr);
  3020. atomic_dec(&rdev->mr_count);
  3021. return rc;
  3022. }
  3023. static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
  3024. {
  3025. struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
  3026. if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
  3027. return -ENOMEM;
  3028. mr->pages[mr->npages++] = addr;
  3029. return 0;
  3030. }
  3031. int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
  3032. unsigned int *sg_offset)
  3033. {
  3034. struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
  3035. mr->npages = 0;
  3036. return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
  3037. }
  3038. struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
  3039. u32 max_num_sg)
  3040. {
  3041. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  3042. struct bnxt_re_dev *rdev = pd->rdev;
  3043. struct bnxt_re_mr *mr = NULL;
  3044. int rc;
  3045. if (type != IB_MR_TYPE_MEM_REG) {
  3046. dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
  3047. return ERR_PTR(-EINVAL);
  3048. }
  3049. if (max_num_sg > MAX_PBL_LVL_1_PGS)
  3050. return ERR_PTR(-EINVAL);
  3051. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  3052. if (!mr)
  3053. return ERR_PTR(-ENOMEM);
  3054. mr->rdev = rdev;
  3055. mr->qplib_mr.pd = &pd->qplib_pd;
  3056. mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
  3057. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
  3058. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  3059. if (rc)
  3060. goto bail;
  3061. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  3062. mr->ib_mr.rkey = mr->ib_mr.lkey;
  3063. mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
  3064. if (!mr->pages) {
  3065. rc = -ENOMEM;
  3066. goto fail;
  3067. }
  3068. rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
  3069. &mr->qplib_frpl, max_num_sg);
  3070. if (rc) {
  3071. dev_err(rdev_to_dev(rdev),
  3072. "Failed to allocate HW FR page list");
  3073. goto fail_mr;
  3074. }
  3075. atomic_inc(&rdev->mr_count);
  3076. return &mr->ib_mr;
  3077. fail_mr:
  3078. kfree(mr->pages);
  3079. fail:
  3080. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  3081. bail:
  3082. kfree(mr);
  3083. return ERR_PTR(rc);
  3084. }
  3085. struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
  3086. struct ib_udata *udata)
  3087. {
  3088. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  3089. struct bnxt_re_dev *rdev = pd->rdev;
  3090. struct bnxt_re_mw *mw;
  3091. int rc;
  3092. mw = kzalloc(sizeof(*mw), GFP_KERNEL);
  3093. if (!mw)
  3094. return ERR_PTR(-ENOMEM);
  3095. mw->rdev = rdev;
  3096. mw->qplib_mw.pd = &pd->qplib_pd;
  3097. mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
  3098. CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
  3099. CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
  3100. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
  3101. if (rc) {
  3102. dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
  3103. goto fail;
  3104. }
  3105. mw->ib_mw.rkey = mw->qplib_mw.rkey;
  3106. atomic_inc(&rdev->mw_count);
  3107. return &mw->ib_mw;
  3108. fail:
  3109. kfree(mw);
  3110. return ERR_PTR(rc);
  3111. }
  3112. int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
  3113. {
  3114. struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
  3115. struct bnxt_re_dev *rdev = mw->rdev;
  3116. int rc;
  3117. rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
  3118. if (rc) {
  3119. dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
  3120. return rc;
  3121. }
  3122. kfree(mw);
  3123. atomic_dec(&rdev->mw_count);
  3124. return rc;
  3125. }
  3126. static int bnxt_re_page_size_ok(int page_shift)
  3127. {
  3128. switch (page_shift) {
  3129. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K:
  3130. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K:
  3131. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K:
  3132. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M:
  3133. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K:
  3134. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M:
  3135. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M:
  3136. case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G:
  3137. return 1;
  3138. default:
  3139. return 0;
  3140. }
  3141. }
  3142. static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig,
  3143. int page_shift)
  3144. {
  3145. u64 *pbl_tbl = pbl_tbl_orig;
  3146. u64 paddr;
  3147. u64 page_mask = (1ULL << page_shift) - 1;
  3148. int i, pages;
  3149. struct scatterlist *sg;
  3150. int entry;
  3151. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  3152. pages = sg_dma_len(sg) >> PAGE_SHIFT;
  3153. for (i = 0; i < pages; i++) {
  3154. paddr = sg_dma_address(sg) + (i << PAGE_SHIFT);
  3155. if (pbl_tbl == pbl_tbl_orig)
  3156. *pbl_tbl++ = paddr & ~page_mask;
  3157. else if ((paddr & page_mask) == 0)
  3158. *pbl_tbl++ = paddr;
  3159. }
  3160. }
  3161. return pbl_tbl - pbl_tbl_orig;
  3162. }
  3163. /* uverbs */
  3164. struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
  3165. u64 virt_addr, int mr_access_flags,
  3166. struct ib_udata *udata)
  3167. {
  3168. struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
  3169. struct bnxt_re_dev *rdev = pd->rdev;
  3170. struct bnxt_re_mr *mr;
  3171. struct ib_umem *umem;
  3172. u64 *pbl_tbl = NULL;
  3173. int umem_pgs, page_shift, rc;
  3174. if (length > BNXT_RE_MAX_MR_SIZE) {
  3175. dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n",
  3176. length, BNXT_RE_MAX_MR_SIZE);
  3177. return ERR_PTR(-ENOMEM);
  3178. }
  3179. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  3180. if (!mr)
  3181. return ERR_PTR(-ENOMEM);
  3182. mr->rdev = rdev;
  3183. mr->qplib_mr.pd = &pd->qplib_pd;
  3184. mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
  3185. mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
  3186. rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
  3187. if (rc) {
  3188. dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
  3189. goto free_mr;
  3190. }
  3191. /* The fixed portion of the rkey is the same as the lkey */
  3192. mr->ib_mr.rkey = mr->qplib_mr.rkey;
  3193. umem = ib_umem_get(ib_pd->uobject->context, start, length,
  3194. mr_access_flags, 0);
  3195. if (IS_ERR(umem)) {
  3196. dev_err(rdev_to_dev(rdev), "Failed to get umem");
  3197. rc = -EFAULT;
  3198. goto free_mrw;
  3199. }
  3200. mr->ib_umem = umem;
  3201. mr->qplib_mr.va = virt_addr;
  3202. umem_pgs = ib_umem_page_count(umem);
  3203. if (!umem_pgs) {
  3204. dev_err(rdev_to_dev(rdev), "umem is invalid!");
  3205. rc = -EINVAL;
  3206. goto free_umem;
  3207. }
  3208. mr->qplib_mr.total_size = length;
  3209. pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
  3210. if (!pbl_tbl) {
  3211. rc = -ENOMEM;
  3212. goto free_umem;
  3213. }
  3214. page_shift = umem->page_shift;
  3215. if (!bnxt_re_page_size_ok(page_shift)) {
  3216. dev_err(rdev_to_dev(rdev), "umem page size unsupported!");
  3217. rc = -EFAULT;
  3218. goto fail;
  3219. }
  3220. if (!umem->hugetlb && length > BNXT_RE_MAX_MR_SIZE_LOW) {
  3221. dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu",
  3222. length, (u64)BNXT_RE_MAX_MR_SIZE_LOW);
  3223. rc = -EINVAL;
  3224. goto fail;
  3225. }
  3226. if (umem->hugetlb && length > BNXT_RE_PAGE_SIZE_2M) {
  3227. page_shift = BNXT_RE_PAGE_SHIFT_2M;
  3228. dev_warn(rdev_to_dev(rdev), "umem hugetlb set page_size %x",
  3229. 1 << page_shift);
  3230. }
  3231. /* Map umem buf ptrs to the PBL */
  3232. umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift);
  3233. rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl,
  3234. umem_pgs, false, 1 << page_shift);
  3235. if (rc) {
  3236. dev_err(rdev_to_dev(rdev), "Failed to register user MR");
  3237. goto fail;
  3238. }
  3239. kfree(pbl_tbl);
  3240. mr->ib_mr.lkey = mr->qplib_mr.lkey;
  3241. mr->ib_mr.rkey = mr->qplib_mr.lkey;
  3242. atomic_inc(&rdev->mr_count);
  3243. return &mr->ib_mr;
  3244. fail:
  3245. kfree(pbl_tbl);
  3246. free_umem:
  3247. ib_umem_release(umem);
  3248. free_mrw:
  3249. bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
  3250. free_mr:
  3251. kfree(mr);
  3252. return ERR_PTR(rc);
  3253. }
  3254. struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev,
  3255. struct ib_udata *udata)
  3256. {
  3257. struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
  3258. struct bnxt_re_uctx_resp resp;
  3259. struct bnxt_re_ucontext *uctx;
  3260. struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
  3261. int rc;
  3262. dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
  3263. ibdev->uverbs_abi_ver);
  3264. if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
  3265. dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
  3266. BNXT_RE_ABI_VERSION);
  3267. return ERR_PTR(-EPERM);
  3268. }
  3269. uctx = kzalloc(sizeof(*uctx), GFP_KERNEL);
  3270. if (!uctx)
  3271. return ERR_PTR(-ENOMEM);
  3272. uctx->rdev = rdev;
  3273. uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
  3274. if (!uctx->shpg) {
  3275. rc = -ENOMEM;
  3276. goto fail;
  3277. }
  3278. spin_lock_init(&uctx->sh_lock);
  3279. resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
  3280. resp.max_qp = rdev->qplib_ctx.qpc_count;
  3281. resp.pg_size = PAGE_SIZE;
  3282. resp.cqe_sz = sizeof(struct cq_base);
  3283. resp.max_cqd = dev_attr->max_cq_wqes;
  3284. resp.rsvd = 0;
  3285. rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
  3286. if (rc) {
  3287. dev_err(rdev_to_dev(rdev), "Failed to copy user context");
  3288. rc = -EFAULT;
  3289. goto cfail;
  3290. }
  3291. return &uctx->ib_uctx;
  3292. cfail:
  3293. free_page((unsigned long)uctx->shpg);
  3294. uctx->shpg = NULL;
  3295. fail:
  3296. kfree(uctx);
  3297. return ERR_PTR(rc);
  3298. }
  3299. int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
  3300. {
  3301. struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
  3302. struct bnxt_re_ucontext,
  3303. ib_uctx);
  3304. struct bnxt_re_dev *rdev = uctx->rdev;
  3305. int rc = 0;
  3306. if (uctx->shpg)
  3307. free_page((unsigned long)uctx->shpg);
  3308. if (uctx->dpi.dbr) {
  3309. /* Free DPI only if this is the first PD allocated by the
  3310. * application and mark the context dpi as NULL
  3311. */
  3312. rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
  3313. &rdev->qplib_res.dpi_tbl,
  3314. &uctx->dpi);
  3315. if (rc)
  3316. dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!");
  3317. /* Don't fail, continue*/
  3318. uctx->dpi.dbr = NULL;
  3319. }
  3320. kfree(uctx);
  3321. return 0;
  3322. }
  3323. /* Helper function to mmap the virtual memory from user app */
  3324. int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
  3325. {
  3326. struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
  3327. struct bnxt_re_ucontext,
  3328. ib_uctx);
  3329. struct bnxt_re_dev *rdev = uctx->rdev;
  3330. u64 pfn;
  3331. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  3332. return -EINVAL;
  3333. if (vma->vm_pgoff) {
  3334. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  3335. if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  3336. PAGE_SIZE, vma->vm_page_prot)) {
  3337. dev_err(rdev_to_dev(rdev), "Failed to map DPI");
  3338. return -EAGAIN;
  3339. }
  3340. } else {
  3341. pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
  3342. if (remap_pfn_range(vma, vma->vm_start,
  3343. pfn, PAGE_SIZE, vma->vm_page_prot)) {
  3344. dev_err(rdev_to_dev(rdev),
  3345. "Failed to map shared page");
  3346. return -EAGAIN;
  3347. }
  3348. }
  3349. return 0;
  3350. }