img-spdif-out.c 12 KB

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  1. /*
  2. * IMG SPDIF output controller driver
  3. *
  4. * Copyright (C) 2015 Imagination Technologies Ltd.
  5. *
  6. * Author: Damien Horsley <Damien.Horsley@imgtec.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2, as published by the Free Software Foundation.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/reset.h>
  20. #include <sound/core.h>
  21. #include <sound/dmaengine_pcm.h>
  22. #include <sound/initval.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #define IMG_SPDIF_OUT_TX_FIFO 0x0
  27. #define IMG_SPDIF_OUT_CTL 0x4
  28. #define IMG_SPDIF_OUT_CTL_FS_MASK BIT(4)
  29. #define IMG_SPDIF_OUT_CTL_CLK_MASK BIT(2)
  30. #define IMG_SPDIF_OUT_CTL_SRT_MASK BIT(0)
  31. #define IMG_SPDIF_OUT_CSL 0x14
  32. #define IMG_SPDIF_OUT_CSH_UV 0x18
  33. #define IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT 0
  34. #define IMG_SPDIF_OUT_CSH_UV_CSH_MASK 0xff
  35. struct img_spdif_out {
  36. spinlock_t lock;
  37. void __iomem *base;
  38. struct clk *clk_sys;
  39. struct clk *clk_ref;
  40. struct snd_dmaengine_dai_dma_data dma_data;
  41. struct device *dev;
  42. struct reset_control *rst;
  43. u32 suspend_ctl;
  44. u32 suspend_csl;
  45. u32 suspend_csh;
  46. };
  47. static int img_spdif_out_runtime_suspend(struct device *dev)
  48. {
  49. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  50. clk_disable_unprepare(spdif->clk_ref);
  51. clk_disable_unprepare(spdif->clk_sys);
  52. return 0;
  53. }
  54. static int img_spdif_out_runtime_resume(struct device *dev)
  55. {
  56. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  57. int ret;
  58. ret = clk_prepare_enable(spdif->clk_sys);
  59. if (ret) {
  60. dev_err(dev, "clk_enable failed: %d\n", ret);
  61. return ret;
  62. }
  63. ret = clk_prepare_enable(spdif->clk_ref);
  64. if (ret) {
  65. dev_err(dev, "clk_enable failed: %d\n", ret);
  66. clk_disable_unprepare(spdif->clk_sys);
  67. return ret;
  68. }
  69. return 0;
  70. }
  71. static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val,
  72. u32 reg)
  73. {
  74. writel(val, spdif->base + reg);
  75. }
  76. static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg)
  77. {
  78. return readl(spdif->base + reg);
  79. }
  80. static void img_spdif_out_reset(struct img_spdif_out *spdif)
  81. {
  82. u32 ctl, status_low, status_high;
  83. ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL) &
  84. ~IMG_SPDIF_OUT_CTL_SRT_MASK;
  85. status_low = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  86. status_high = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  87. reset_control_assert(spdif->rst);
  88. reset_control_deassert(spdif->rst);
  89. img_spdif_out_writel(spdif, ctl, IMG_SPDIF_OUT_CTL);
  90. img_spdif_out_writel(spdif, status_low, IMG_SPDIF_OUT_CSL);
  91. img_spdif_out_writel(spdif, status_high, IMG_SPDIF_OUT_CSH_UV);
  92. }
  93. static int img_spdif_out_info(struct snd_kcontrol *kcontrol,
  94. struct snd_ctl_elem_info *uinfo)
  95. {
  96. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  97. uinfo->count = 1;
  98. return 0;
  99. }
  100. static int img_spdif_out_get_status_mask(struct snd_kcontrol *kcontrol,
  101. struct snd_ctl_elem_value *ucontrol)
  102. {
  103. ucontrol->value.iec958.status[0] = 0xff;
  104. ucontrol->value.iec958.status[1] = 0xff;
  105. ucontrol->value.iec958.status[2] = 0xff;
  106. ucontrol->value.iec958.status[3] = 0xff;
  107. ucontrol->value.iec958.status[4] = 0xff;
  108. return 0;
  109. }
  110. static int img_spdif_out_get_status(struct snd_kcontrol *kcontrol,
  111. struct snd_ctl_elem_value *ucontrol)
  112. {
  113. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  114. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
  115. u32 reg;
  116. unsigned long flags;
  117. spin_lock_irqsave(&spdif->lock, flags);
  118. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  119. ucontrol->value.iec958.status[0] = reg & 0xff;
  120. ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
  121. ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
  122. ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
  123. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  124. ucontrol->value.iec958.status[4] =
  125. (reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >>
  126. IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
  127. spin_unlock_irqrestore(&spdif->lock, flags);
  128. return 0;
  129. }
  130. static int img_spdif_out_set_status(struct snd_kcontrol *kcontrol,
  131. struct snd_ctl_elem_value *ucontrol)
  132. {
  133. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  134. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
  135. u32 reg;
  136. unsigned long flags;
  137. reg = ((u32)ucontrol->value.iec958.status[3] << 24);
  138. reg |= ((u32)ucontrol->value.iec958.status[2] << 16);
  139. reg |= ((u32)ucontrol->value.iec958.status[1] << 8);
  140. reg |= (u32)ucontrol->value.iec958.status[0];
  141. spin_lock_irqsave(&spdif->lock, flags);
  142. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL);
  143. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  144. reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK;
  145. reg |= (u32)ucontrol->value.iec958.status[4] <<
  146. IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
  147. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV);
  148. spin_unlock_irqrestore(&spdif->lock, flags);
  149. return 0;
  150. }
  151. static struct snd_kcontrol_new img_spdif_out_controls[] = {
  152. {
  153. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  154. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  155. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
  156. .info = img_spdif_out_info,
  157. .get = img_spdif_out_get_status_mask
  158. },
  159. {
  160. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  161. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  162. .info = img_spdif_out_info,
  163. .get = img_spdif_out_get_status,
  164. .put = img_spdif_out_set_status
  165. }
  166. };
  167. static int img_spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
  168. struct snd_soc_dai *dai)
  169. {
  170. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  171. u32 reg;
  172. unsigned long flags;
  173. switch (cmd) {
  174. case SNDRV_PCM_TRIGGER_START:
  175. case SNDRV_PCM_TRIGGER_RESUME:
  176. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  177. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  178. reg |= IMG_SPDIF_OUT_CTL_SRT_MASK;
  179. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
  180. break;
  181. case SNDRV_PCM_TRIGGER_STOP:
  182. case SNDRV_PCM_TRIGGER_SUSPEND:
  183. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  184. spin_lock_irqsave(&spdif->lock, flags);
  185. img_spdif_out_reset(spdif);
  186. spin_unlock_irqrestore(&spdif->lock, flags);
  187. break;
  188. default:
  189. return -EINVAL;
  190. }
  191. return 0;
  192. }
  193. static int img_spdif_out_hw_params(struct snd_pcm_substream *substream,
  194. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  195. {
  196. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  197. unsigned int channels;
  198. long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
  199. u32 reg;
  200. snd_pcm_format_t format;
  201. rate = params_rate(params);
  202. format = params_format(params);
  203. channels = params_channels(params);
  204. dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
  205. rate, channels, format);
  206. if (format != SNDRV_PCM_FORMAT_S32_LE)
  207. return -EINVAL;
  208. if (channels != 2)
  209. return -EINVAL;
  210. pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
  211. if (pre_div_a < 0)
  212. return pre_div_a;
  213. pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
  214. if (pre_div_b < 0)
  215. return pre_div_b;
  216. diff_a = abs((pre_div_a / 256) - rate);
  217. diff_b = abs((pre_div_b / 384) - rate);
  218. /* If diffs are equal, use lower clock rate */
  219. if (diff_a > diff_b)
  220. clk_set_rate(spdif->clk_ref, pre_div_b);
  221. else
  222. clk_set_rate(spdif->clk_ref, pre_div_a);
  223. /*
  224. * Another driver (eg machine driver) may have rejected the above
  225. * change. Get the current rate and set the register bit according to
  226. * the new min diff
  227. */
  228. clk_rate = clk_get_rate(spdif->clk_ref);
  229. diff_a = abs((clk_rate / 256) - rate);
  230. diff_b = abs((clk_rate / 384) - rate);
  231. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  232. if (diff_a <= diff_b)
  233. reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK;
  234. else
  235. reg |= IMG_SPDIF_OUT_CTL_CLK_MASK;
  236. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
  237. return 0;
  238. }
  239. static const struct snd_soc_dai_ops img_spdif_out_dai_ops = {
  240. .trigger = img_spdif_out_trigger,
  241. .hw_params = img_spdif_out_hw_params
  242. };
  243. static int img_spdif_out_dai_probe(struct snd_soc_dai *dai)
  244. {
  245. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  246. snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
  247. snd_soc_add_dai_controls(dai, img_spdif_out_controls,
  248. ARRAY_SIZE(img_spdif_out_controls));
  249. return 0;
  250. }
  251. static struct snd_soc_dai_driver img_spdif_out_dai = {
  252. .probe = img_spdif_out_dai_probe,
  253. .playback = {
  254. .channels_min = 2,
  255. .channels_max = 2,
  256. .rates = SNDRV_PCM_RATE_8000_192000,
  257. .formats = SNDRV_PCM_FMTBIT_S32_LE
  258. },
  259. .ops = &img_spdif_out_dai_ops
  260. };
  261. static const struct snd_soc_component_driver img_spdif_out_component = {
  262. .name = "img-spdif-out"
  263. };
  264. static int img_spdif_out_probe(struct platform_device *pdev)
  265. {
  266. struct img_spdif_out *spdif;
  267. struct resource *res;
  268. void __iomem *base;
  269. int ret;
  270. struct device *dev = &pdev->dev;
  271. spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
  272. if (!spdif)
  273. return -ENOMEM;
  274. platform_set_drvdata(pdev, spdif);
  275. spdif->dev = &pdev->dev;
  276. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  277. base = devm_ioremap_resource(&pdev->dev, res);
  278. if (IS_ERR(base))
  279. return PTR_ERR(base);
  280. spdif->base = base;
  281. spdif->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
  282. if (IS_ERR(spdif->rst)) {
  283. if (PTR_ERR(spdif->rst) != -EPROBE_DEFER)
  284. dev_err(&pdev->dev, "No top level reset found\n");
  285. return PTR_ERR(spdif->rst);
  286. }
  287. spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
  288. if (IS_ERR(spdif->clk_sys)) {
  289. if (PTR_ERR(spdif->clk_sys) != -EPROBE_DEFER)
  290. dev_err(dev, "Failed to acquire clock 'sys'\n");
  291. return PTR_ERR(spdif->clk_sys);
  292. }
  293. spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
  294. if (IS_ERR(spdif->clk_ref)) {
  295. if (PTR_ERR(spdif->clk_ref) != -EPROBE_DEFER)
  296. dev_err(dev, "Failed to acquire clock 'ref'\n");
  297. return PTR_ERR(spdif->clk_ref);
  298. }
  299. pm_runtime_enable(&pdev->dev);
  300. if (!pm_runtime_enabled(&pdev->dev)) {
  301. ret = img_spdif_out_runtime_resume(&pdev->dev);
  302. if (ret)
  303. goto err_pm_disable;
  304. }
  305. ret = pm_runtime_get_sync(&pdev->dev);
  306. if (ret < 0)
  307. goto err_suspend;
  308. img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
  309. IMG_SPDIF_OUT_CTL);
  310. img_spdif_out_reset(spdif);
  311. pm_runtime_put(&pdev->dev);
  312. spin_lock_init(&spdif->lock);
  313. spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
  314. spdif->dma_data.addr_width = 4;
  315. spdif->dma_data.maxburst = 4;
  316. ret = devm_snd_soc_register_component(&pdev->dev,
  317. &img_spdif_out_component,
  318. &img_spdif_out_dai, 1);
  319. if (ret)
  320. goto err_suspend;
  321. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  322. if (ret)
  323. goto err_suspend;
  324. dev_dbg(&pdev->dev, "Probe successful\n");
  325. return 0;
  326. err_suspend:
  327. if (!pm_runtime_status_suspended(&pdev->dev))
  328. img_spdif_out_runtime_suspend(&pdev->dev);
  329. err_pm_disable:
  330. pm_runtime_disable(&pdev->dev);
  331. return ret;
  332. }
  333. static int img_spdif_out_dev_remove(struct platform_device *pdev)
  334. {
  335. pm_runtime_disable(&pdev->dev);
  336. if (!pm_runtime_status_suspended(&pdev->dev))
  337. img_spdif_out_runtime_suspend(&pdev->dev);
  338. return 0;
  339. }
  340. #ifdef CONFIG_PM_SLEEP
  341. static int img_spdif_out_suspend(struct device *dev)
  342. {
  343. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  344. int ret;
  345. if (pm_runtime_status_suspended(dev)) {
  346. ret = img_spdif_out_runtime_resume(dev);
  347. if (ret)
  348. return ret;
  349. }
  350. spdif->suspend_ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  351. spdif->suspend_csl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  352. spdif->suspend_csh = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  353. img_spdif_out_runtime_suspend(dev);
  354. return 0;
  355. }
  356. static int img_spdif_out_resume(struct device *dev)
  357. {
  358. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  359. int ret;
  360. ret = img_spdif_out_runtime_resume(dev);
  361. if (ret)
  362. return ret;
  363. img_spdif_out_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_OUT_CTL);
  364. img_spdif_out_writel(spdif, spdif->suspend_csl, IMG_SPDIF_OUT_CSL);
  365. img_spdif_out_writel(spdif, spdif->suspend_csh, IMG_SPDIF_OUT_CSH_UV);
  366. if (pm_runtime_status_suspended(dev))
  367. img_spdif_out_runtime_suspend(dev);
  368. return 0;
  369. }
  370. #endif
  371. static const struct of_device_id img_spdif_out_of_match[] = {
  372. { .compatible = "img,spdif-out" },
  373. {}
  374. };
  375. MODULE_DEVICE_TABLE(of, img_spdif_out_of_match);
  376. static const struct dev_pm_ops img_spdif_out_pm_ops = {
  377. SET_RUNTIME_PM_OPS(img_spdif_out_runtime_suspend,
  378. img_spdif_out_runtime_resume, NULL)
  379. SET_SYSTEM_SLEEP_PM_OPS(img_spdif_out_suspend, img_spdif_out_resume)
  380. };
  381. static struct platform_driver img_spdif_out_driver = {
  382. .driver = {
  383. .name = "img-spdif-out",
  384. .of_match_table = img_spdif_out_of_match,
  385. .pm = &img_spdif_out_pm_ops
  386. },
  387. .probe = img_spdif_out_probe,
  388. .remove = img_spdif_out_dev_remove
  389. };
  390. module_platform_driver(img_spdif_out_driver);
  391. MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
  392. MODULE_DESCRIPTION("IMG SPDIF Output driver");
  393. MODULE_LICENSE("GPL v2");