axg-tdmout.c 7.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. #include <linux/module.h>
  6. #include <linux/of_platform.h>
  7. #include <linux/regmap.h>
  8. #include <sound/soc.h>
  9. #include <sound/soc-dai.h>
  10. #include "axg-tdm-formatter.h"
  11. #define TDMOUT_CTRL0 0x00
  12. #define TDMOUT_CTRL0_BITNUM_MASK GENMASK(4, 0)
  13. #define TDMOUT_CTRL0_BITNUM(x) ((x) << 0)
  14. #define TDMOUT_CTRL0_SLOTNUM_MASK GENMASK(9, 5)
  15. #define TDMOUT_CTRL0_SLOTNUM(x) ((x) << 5)
  16. #define TDMOUT_CTRL0_INIT_BITNUM_MASK GENMASK(19, 15)
  17. #define TDMOUT_CTRL0_INIT_BITNUM(x) ((x) << 15)
  18. #define TDMOUT_CTRL0_ENABLE BIT(31)
  19. #define TDMOUT_CTRL0_RST_OUT BIT(29)
  20. #define TDMOUT_CTRL0_RST_IN BIT(28)
  21. #define TDMOUT_CTRL1 0x04
  22. #define TDMOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
  23. #define TDMOUT_CTRL1_TYPE(x) ((x) << 4)
  24. #define TDMOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)
  25. #define TDMOUT_CTRL1_MSB_POS(x) ((x) << 8)
  26. #define TDMOUT_CTRL1_SEL_SHIFT 24
  27. #define TDMOUT_CTRL1_GAIN_EN 26
  28. #define TDMOUT_CTRL1_WS_INV BIT(28)
  29. #define TDMOUT_SWAP 0x08
  30. #define TDMOUT_MASK0 0x0c
  31. #define TDMOUT_MASK1 0x10
  32. #define TDMOUT_MASK2 0x14
  33. #define TDMOUT_MASK3 0x18
  34. #define TDMOUT_STAT 0x1c
  35. #define TDMOUT_GAIN0 0x20
  36. #define TDMOUT_GAIN1 0x24
  37. #define TDMOUT_MUTE_VAL 0x28
  38. #define TDMOUT_MUTE0 0x2c
  39. #define TDMOUT_MUTE1 0x30
  40. #define TDMOUT_MUTE2 0x34
  41. #define TDMOUT_MUTE3 0x38
  42. #define TDMOUT_MASK_VAL 0x3c
  43. static const struct regmap_config axg_tdmout_regmap_cfg = {
  44. .reg_bits = 32,
  45. .val_bits = 32,
  46. .reg_stride = 4,
  47. .max_register = TDMOUT_MASK_VAL,
  48. };
  49. static const struct snd_kcontrol_new axg_tdmout_controls[] = {
  50. SOC_DOUBLE("Lane 0 Volume", TDMOUT_GAIN0, 0, 8, 255, 0),
  51. SOC_DOUBLE("Lane 1 Volume", TDMOUT_GAIN0, 16, 24, 255, 0),
  52. SOC_DOUBLE("Lane 2 Volume", TDMOUT_GAIN1, 0, 8, 255, 0),
  53. SOC_DOUBLE("Lane 3 Volume", TDMOUT_GAIN1, 16, 24, 255, 0),
  54. SOC_SINGLE("Gain Enable Switch", TDMOUT_CTRL1,
  55. TDMOUT_CTRL1_GAIN_EN, 1, 0),
  56. };
  57. static const char * const tdmout_sel_texts[] = {
  58. "IN 0", "IN 1", "IN 2",
  59. };
  60. static SOC_ENUM_SINGLE_DECL(axg_tdmout_sel_enum, TDMOUT_CTRL1,
  61. TDMOUT_CTRL1_SEL_SHIFT, tdmout_sel_texts);
  62. static const struct snd_kcontrol_new axg_tdmout_in_mux =
  63. SOC_DAPM_ENUM("Input Source", axg_tdmout_sel_enum);
  64. static struct snd_soc_dai *
  65. axg_tdmout_get_be(struct snd_soc_dapm_widget *w)
  66. {
  67. struct snd_soc_dapm_path *p = NULL;
  68. struct snd_soc_dai *be;
  69. snd_soc_dapm_widget_for_each_sink_path(w, p) {
  70. if (!p->connect)
  71. continue;
  72. if (p->sink->id == snd_soc_dapm_dai_in)
  73. return (struct snd_soc_dai *)p->sink->priv;
  74. be = axg_tdmout_get_be(p->sink);
  75. if (be)
  76. return be;
  77. }
  78. return NULL;
  79. }
  80. static struct axg_tdm_stream *
  81. axg_tdmout_get_tdm_stream(struct snd_soc_dapm_widget *w)
  82. {
  83. struct snd_soc_dai *be = axg_tdmout_get_be(w);
  84. if (!be)
  85. return NULL;
  86. return be->playback_dma_data;
  87. }
  88. static void axg_tdmout_enable(struct regmap *map)
  89. {
  90. /* Apply both reset */
  91. regmap_update_bits(map, TDMOUT_CTRL0,
  92. TDMOUT_CTRL0_RST_OUT | TDMOUT_CTRL0_RST_IN, 0);
  93. /* Clear out reset before in reset */
  94. regmap_update_bits(map, TDMOUT_CTRL0,
  95. TDMOUT_CTRL0_RST_OUT, TDMOUT_CTRL0_RST_OUT);
  96. regmap_update_bits(map, TDMOUT_CTRL0,
  97. TDMOUT_CTRL0_RST_IN, TDMOUT_CTRL0_RST_IN);
  98. /* Actually enable tdmout */
  99. regmap_update_bits(map, TDMOUT_CTRL0,
  100. TDMOUT_CTRL0_ENABLE, TDMOUT_CTRL0_ENABLE);
  101. }
  102. static void axg_tdmout_disable(struct regmap *map)
  103. {
  104. regmap_update_bits(map, TDMOUT_CTRL0, TDMOUT_CTRL0_ENABLE, 0);
  105. }
  106. static int axg_tdmout_prepare(struct regmap *map, struct axg_tdm_stream *ts)
  107. {
  108. unsigned int val = 0;
  109. /* Set the stream skew */
  110. switch (ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  111. case SND_SOC_DAIFMT_I2S:
  112. case SND_SOC_DAIFMT_DSP_A:
  113. val |= TDMOUT_CTRL0_INIT_BITNUM(1);
  114. break;
  115. case SND_SOC_DAIFMT_LEFT_J:
  116. case SND_SOC_DAIFMT_DSP_B:
  117. val |= TDMOUT_CTRL0_INIT_BITNUM(2);
  118. break;
  119. default:
  120. pr_err("Unsupported format: %u\n",
  121. ts->iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  122. return -EINVAL;
  123. }
  124. /* Set the slot width */
  125. val |= TDMOUT_CTRL0_BITNUM(ts->iface->slot_width - 1);
  126. /* Set the slot number */
  127. val |= TDMOUT_CTRL0_SLOTNUM(ts->iface->slots - 1);
  128. regmap_update_bits(map, TDMOUT_CTRL0,
  129. TDMOUT_CTRL0_INIT_BITNUM_MASK |
  130. TDMOUT_CTRL0_BITNUM_MASK |
  131. TDMOUT_CTRL0_SLOTNUM_MASK, val);
  132. /* Set the sample width */
  133. val = TDMOUT_CTRL1_MSB_POS(ts->width - 1);
  134. /* FIFO data are arranged in chunks of 64bits */
  135. switch (ts->physical_width) {
  136. case 8:
  137. /* 8 samples of 8 bits */
  138. val |= TDMOUT_CTRL1_TYPE(0);
  139. break;
  140. case 16:
  141. /* 4 samples of 16 bits - right justified */
  142. val |= TDMOUT_CTRL1_TYPE(2);
  143. break;
  144. case 32:
  145. /* 2 samples of 32 bits - right justified */
  146. val |= TDMOUT_CTRL1_TYPE(4);
  147. break;
  148. default:
  149. pr_err("Unsupported physical width: %u\n",
  150. ts->physical_width);
  151. return -EINVAL;
  152. }
  153. /* If the sample clock is inverted, invert it back for the formatter */
  154. if (axg_tdm_lrclk_invert(ts->iface->fmt))
  155. val |= TDMOUT_CTRL1_WS_INV;
  156. regmap_update_bits(map, TDMOUT_CTRL1,
  157. (TDMOUT_CTRL1_TYPE_MASK | TDMOUT_CTRL1_MSB_POS_MASK |
  158. TDMOUT_CTRL1_WS_INV), val);
  159. /* Set static swap mask configuration */
  160. regmap_write(map, TDMOUT_SWAP, 0x76543210);
  161. return axg_tdm_formatter_set_channel_masks(map, ts, TDMOUT_MASK0);
  162. }
  163. static const struct snd_soc_dapm_widget axg_tdmout_dapm_widgets[] = {
  164. SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
  165. SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  166. SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  167. SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_tdmout_in_mux),
  168. SND_SOC_DAPM_PGA_E("ENC", SND_SOC_NOPM, 0, 0, NULL, 0,
  169. axg_tdm_formatter_event,
  170. (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD)),
  171. SND_SOC_DAPM_AIF_OUT("OUT", NULL, 0, SND_SOC_NOPM, 0, 0),
  172. };
  173. static const struct snd_soc_dapm_route axg_tdmout_dapm_routes[] = {
  174. { "SRC SEL", "IN 0", "IN 0" },
  175. { "SRC SEL", "IN 1", "IN 1" },
  176. { "SRC SEL", "IN 2", "IN 2" },
  177. { "ENC", NULL, "SRC SEL" },
  178. { "OUT", NULL, "ENC" },
  179. };
  180. static const struct snd_soc_component_driver axg_tdmout_component_drv = {
  181. .controls = axg_tdmout_controls,
  182. .num_controls = ARRAY_SIZE(axg_tdmout_controls),
  183. .dapm_widgets = axg_tdmout_dapm_widgets,
  184. .num_dapm_widgets = ARRAY_SIZE(axg_tdmout_dapm_widgets),
  185. .dapm_routes = axg_tdmout_dapm_routes,
  186. .num_dapm_routes = ARRAY_SIZE(axg_tdmout_dapm_routes),
  187. };
  188. static const struct axg_tdm_formatter_ops axg_tdmout_ops = {
  189. .get_stream = axg_tdmout_get_tdm_stream,
  190. .prepare = axg_tdmout_prepare,
  191. .enable = axg_tdmout_enable,
  192. .disable = axg_tdmout_disable,
  193. };
  194. static const struct axg_tdm_formatter_driver axg_tdmout_drv = {
  195. .component_drv = &axg_tdmout_component_drv,
  196. .regmap_cfg = &axg_tdmout_regmap_cfg,
  197. .ops = &axg_tdmout_ops,
  198. .invert_sclk = true,
  199. };
  200. static const struct of_device_id axg_tdmout_of_match[] = {
  201. {
  202. .compatible = "amlogic,axg-tdmout",
  203. .data = &axg_tdmout_drv,
  204. }, {}
  205. };
  206. MODULE_DEVICE_TABLE(of, axg_tdmout_of_match);
  207. static struct platform_driver axg_tdmout_pdrv = {
  208. .probe = axg_tdm_formatter_probe,
  209. .driver = {
  210. .name = "axg-tdmout",
  211. .of_match_table = axg_tdmout_of_match,
  212. },
  213. };
  214. module_platform_driver(axg_tdmout_pdrv);
  215. MODULE_DESCRIPTION("Amlogic AXG TDM output formatter driver");
  216. MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
  217. MODULE_LICENSE("GPL v2");