sun4i-codec.c 53 KB

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  1. /*
  2. * Copyright 2014 Emilio López <emilio@elopez.com.ar>
  3. * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
  4. * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
  5. * Copyright 2015 Adam Sampson <ats@offog.org>
  6. * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
  7. *
  8. * Based on the Allwinner SDK driver, released under the GPL.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/init.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/of.h>
  27. #include <linux/of_address.h>
  28. #include <linux/of_device.h>
  29. #include <linux/of_platform.h>
  30. #include <linux/clk.h>
  31. #include <linux/regmap.h>
  32. #include <linux/reset.h>
  33. #include <linux/gpio/consumer.h>
  34. #include <sound/core.h>
  35. #include <sound/pcm.h>
  36. #include <sound/pcm_params.h>
  37. #include <sound/soc.h>
  38. #include <sound/tlv.h>
  39. #include <sound/initval.h>
  40. #include <sound/dmaengine_pcm.h>
  41. /* Codec DAC digital controls and FIFO registers */
  42. #define SUN4I_CODEC_DAC_DPC (0x00)
  43. #define SUN4I_CODEC_DAC_DPC_EN_DA (31)
  44. #define SUN4I_CODEC_DAC_DPC_DVOL (12)
  45. #define SUN4I_CODEC_DAC_FIFOC (0x04)
  46. #define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29)
  47. #define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28)
  48. #define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26)
  49. #define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24)
  50. #define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21)
  51. #define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8)
  52. #define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6)
  53. #define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5)
  54. #define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4)
  55. #define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0)
  56. #define SUN4I_CODEC_DAC_FIFOS (0x08)
  57. #define SUN4I_CODEC_DAC_TXDATA (0x0c)
  58. /* Codec DAC side analog signal controls */
  59. #define SUN4I_CODEC_DAC_ACTL (0x10)
  60. #define SUN4I_CODEC_DAC_ACTL_DACAENR (31)
  61. #define SUN4I_CODEC_DAC_ACTL_DACAENL (30)
  62. #define SUN4I_CODEC_DAC_ACTL_MIXEN (29)
  63. #define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15)
  64. #define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14)
  65. #define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13)
  66. #define SUN4I_CODEC_DAC_ACTL_DACPAS (8)
  67. #define SUN4I_CODEC_DAC_ACTL_MIXPAS (7)
  68. #define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6)
  69. #define SUN4I_CODEC_DAC_ACTL_PA_VOL (0)
  70. #define SUN4I_CODEC_DAC_TUNE (0x14)
  71. #define SUN4I_CODEC_DAC_DEBUG (0x18)
  72. /* Codec ADC digital controls and FIFO registers */
  73. #define SUN4I_CODEC_ADC_FIFOC (0x1c)
  74. #define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29)
  75. #define SUN4I_CODEC_ADC_FIFOC_EN_AD (28)
  76. #define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24)
  77. #define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8)
  78. #define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7)
  79. #define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6)
  80. #define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4)
  81. #define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0)
  82. #define SUN4I_CODEC_ADC_FIFOS (0x20)
  83. #define SUN4I_CODEC_ADC_RXDATA (0x24)
  84. /* Codec ADC side analog signal controls */
  85. #define SUN4I_CODEC_ADC_ACTL (0x28)
  86. #define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31)
  87. #define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30)
  88. #define SUN4I_CODEC_ADC_ACTL_PREG1EN (29)
  89. #define SUN4I_CODEC_ADC_ACTL_PREG2EN (28)
  90. #define SUN4I_CODEC_ADC_ACTL_VMICEN (27)
  91. #define SUN4I_CODEC_ADC_ACTL_VADCG (20)
  92. #define SUN4I_CODEC_ADC_ACTL_ADCIS (17)
  93. #define SUN4I_CODEC_ADC_ACTL_PA_EN (4)
  94. #define SUN4I_CODEC_ADC_ACTL_DDE (3)
  95. #define SUN4I_CODEC_ADC_DEBUG (0x2c)
  96. /* FIFO counters */
  97. #define SUN4I_CODEC_DAC_TXCNT (0x30)
  98. #define SUN4I_CODEC_ADC_RXCNT (0x34)
  99. /* Calibration register (sun7i only) */
  100. #define SUN7I_CODEC_AC_DAC_CAL (0x38)
  101. /* Microphone controls (sun7i only) */
  102. #define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c)
  103. /*
  104. * sun6i specific registers
  105. *
  106. * sun6i shares the same digital control and FIFO registers as sun4i,
  107. * but only the DAC digital controls are at the same offset. The others
  108. * have been moved around to accommodate extra analog controls.
  109. */
  110. /* Codec DAC digital controls and FIFO registers */
  111. #define SUN6I_CODEC_ADC_FIFOC (0x10)
  112. #define SUN6I_CODEC_ADC_FIFOC_EN_AD (28)
  113. #define SUN6I_CODEC_ADC_FIFOS (0x14)
  114. #define SUN6I_CODEC_ADC_RXDATA (0x18)
  115. /* Output mixer and gain controls */
  116. #define SUN6I_CODEC_OM_DACA_CTRL (0x20)
  117. #define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31)
  118. #define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30)
  119. #define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29)
  120. #define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28)
  121. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23)
  122. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22)
  123. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21)
  124. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20)
  125. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19)
  126. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18)
  127. #define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17)
  128. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16)
  129. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15)
  130. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14)
  131. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13)
  132. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12)
  133. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11)
  134. #define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10)
  135. #define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9)
  136. #define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8)
  137. #define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7)
  138. #define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6)
  139. #define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0)
  140. #define SUN6I_CODEC_OM_PA_CTRL (0x24)
  141. #define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31)
  142. #define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29)
  143. #define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28)
  144. #define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15)
  145. #define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12)
  146. #define SUN6I_CODEC_OM_PA_CTRL_LINEING (9)
  147. #define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6)
  148. #define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3)
  149. #define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0)
  150. /* Microphone, line out and phone out controls */
  151. #define SUN6I_CODEC_MIC_CTRL (0x28)
  152. #define SUN6I_CODEC_MIC_CTRL_HBIASEN (31)
  153. #define SUN6I_CODEC_MIC_CTRL_MBIASEN (30)
  154. #define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28)
  155. #define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25)
  156. #define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24)
  157. #define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21)
  158. #define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20)
  159. #define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19)
  160. #define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18)
  161. #define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17)
  162. #define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16)
  163. #define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11)
  164. #define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8)
  165. /* ADC mixer controls */
  166. #define SUN6I_CODEC_ADC_ACTL (0x2c)
  167. #define SUN6I_CODEC_ADC_ACTL_ADCREN (31)
  168. #define SUN6I_CODEC_ADC_ACTL_ADCLEN (30)
  169. #define SUN6I_CODEC_ADC_ACTL_ADCRG (27)
  170. #define SUN6I_CODEC_ADC_ACTL_ADCLG (24)
  171. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13)
  172. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12)
  173. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11)
  174. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10)
  175. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9)
  176. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8)
  177. #define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7)
  178. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6)
  179. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5)
  180. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4)
  181. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3)
  182. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2)
  183. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1)
  184. #define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0)
  185. /* Analog performance tuning controls */
  186. #define SUN6I_CODEC_ADDA_TUNE (0x30)
  187. /* Calibration controls */
  188. #define SUN6I_CODEC_CALIBRATION (0x34)
  189. /* FIFO counters */
  190. #define SUN6I_CODEC_DAC_TXCNT (0x40)
  191. #define SUN6I_CODEC_ADC_RXCNT (0x44)
  192. /* headset jack detection and button support registers */
  193. #define SUN6I_CODEC_HMIC_CTL (0x50)
  194. #define SUN6I_CODEC_HMIC_DATA (0x54)
  195. /* TODO sun6i DAP (Digital Audio Processing) bits */
  196. /* FIFO counters moved on A23 */
  197. #define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
  198. #define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
  199. /* TX FIFO moved on H3 */
  200. #define SUN8I_H3_CODEC_DAC_TXDATA (0x20)
  201. #define SUN8I_H3_CODEC_DAC_DBG (0x48)
  202. #define SUN8I_H3_CODEC_ADC_DBG (0x4c)
  203. /* TODO H3 DAP (Digital Audio Processing) bits */
  204. struct sun4i_codec {
  205. struct device *dev;
  206. struct regmap *regmap;
  207. struct clk *clk_apb;
  208. struct clk *clk_module;
  209. struct reset_control *rst;
  210. struct gpio_desc *gpio_pa;
  211. /* ADC_FIFOC register is at different offset on different SoCs */
  212. struct regmap_field *reg_adc_fifoc;
  213. struct snd_dmaengine_dai_dma_data capture_dma_data;
  214. struct snd_dmaengine_dai_dma_data playback_dma_data;
  215. };
  216. static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
  217. {
  218. /* Flush TX FIFO */
  219. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  220. BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
  221. BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
  222. /* Enable DAC DRQ */
  223. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  224. BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
  225. BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
  226. }
  227. static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
  228. {
  229. /* Disable DAC DRQ */
  230. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  231. BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
  232. 0);
  233. }
  234. static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
  235. {
  236. /* Enable ADC DRQ */
  237. regmap_field_update_bits(scodec->reg_adc_fifoc,
  238. BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN),
  239. BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
  240. }
  241. static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
  242. {
  243. /* Disable ADC DRQ */
  244. regmap_field_update_bits(scodec->reg_adc_fifoc,
  245. BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 0);
  246. }
  247. static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
  248. struct snd_soc_dai *dai)
  249. {
  250. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  251. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
  252. switch (cmd) {
  253. case SNDRV_PCM_TRIGGER_START:
  254. case SNDRV_PCM_TRIGGER_RESUME:
  255. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  256. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  257. sun4i_codec_start_playback(scodec);
  258. else
  259. sun4i_codec_start_capture(scodec);
  260. break;
  261. case SNDRV_PCM_TRIGGER_STOP:
  262. case SNDRV_PCM_TRIGGER_SUSPEND:
  263. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  264. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  265. sun4i_codec_stop_playback(scodec);
  266. else
  267. sun4i_codec_stop_capture(scodec);
  268. break;
  269. default:
  270. return -EINVAL;
  271. }
  272. return 0;
  273. }
  274. static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
  275. struct snd_soc_dai *dai)
  276. {
  277. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  278. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
  279. /* Flush RX FIFO */
  280. regmap_field_update_bits(scodec->reg_adc_fifoc,
  281. BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH),
  282. BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH));
  283. /* Set RX FIFO trigger level */
  284. regmap_field_update_bits(scodec->reg_adc_fifoc,
  285. 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
  286. 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
  287. /*
  288. * FIXME: Undocumented in the datasheet, but
  289. * Allwinner's code mentions that it is related
  290. * related to microphone gain
  291. */
  292. if (of_device_is_compatible(scodec->dev->of_node,
  293. "allwinner,sun4i-a10-codec") ||
  294. of_device_is_compatible(scodec->dev->of_node,
  295. "allwinner,sun7i-a20-codec")) {
  296. regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
  297. 0x3 << 25,
  298. 0x1 << 25);
  299. }
  300. if (of_device_is_compatible(scodec->dev->of_node,
  301. "allwinner,sun7i-a20-codec"))
  302. /* FIXME: Undocumented bits */
  303. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE,
  304. 0x3 << 8,
  305. 0x1 << 8);
  306. return 0;
  307. }
  308. static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
  309. struct snd_soc_dai *dai)
  310. {
  311. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  312. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
  313. u32 val;
  314. /* Flush the TX FIFO */
  315. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  316. BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
  317. BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
  318. /* Set TX FIFO Empty Trigger Level */
  319. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  320. 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
  321. 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
  322. if (substream->runtime->rate > 32000)
  323. /* Use 64 bits FIR filter */
  324. val = 0;
  325. else
  326. /* Use 32 bits FIR filter */
  327. val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
  328. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  329. BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
  330. val);
  331. /* Send zeros when we have an underrun */
  332. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  333. BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT),
  334. 0);
  335. return 0;
  336. };
  337. static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
  338. struct snd_soc_dai *dai)
  339. {
  340. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  341. return sun4i_codec_prepare_playback(substream, dai);
  342. return sun4i_codec_prepare_capture(substream, dai);
  343. }
  344. static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
  345. {
  346. unsigned int rate = params_rate(params);
  347. switch (rate) {
  348. case 176400:
  349. case 88200:
  350. case 44100:
  351. case 33075:
  352. case 22050:
  353. case 14700:
  354. case 11025:
  355. case 7350:
  356. return 22579200;
  357. case 192000:
  358. case 96000:
  359. case 48000:
  360. case 32000:
  361. case 24000:
  362. case 16000:
  363. case 12000:
  364. case 8000:
  365. return 24576000;
  366. default:
  367. return 0;
  368. }
  369. }
  370. static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
  371. {
  372. unsigned int rate = params_rate(params);
  373. switch (rate) {
  374. case 192000:
  375. case 176400:
  376. return 6;
  377. case 96000:
  378. case 88200:
  379. return 7;
  380. case 48000:
  381. case 44100:
  382. return 0;
  383. case 32000:
  384. case 33075:
  385. return 1;
  386. case 24000:
  387. case 22050:
  388. return 2;
  389. case 16000:
  390. case 14700:
  391. return 3;
  392. case 12000:
  393. case 11025:
  394. return 4;
  395. case 8000:
  396. case 7350:
  397. return 5;
  398. default:
  399. return -EINVAL;
  400. }
  401. }
  402. static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
  403. struct snd_pcm_hw_params *params,
  404. unsigned int hwrate)
  405. {
  406. /* Set ADC sample rate */
  407. regmap_field_update_bits(scodec->reg_adc_fifoc,
  408. 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
  409. hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
  410. /* Set the number of channels we want to use */
  411. if (params_channels(params) == 1)
  412. regmap_field_update_bits(scodec->reg_adc_fifoc,
  413. BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN),
  414. BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
  415. else
  416. regmap_field_update_bits(scodec->reg_adc_fifoc,
  417. BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN),
  418. 0);
  419. /* Set the number of sample bits to either 16 or 24 bits */
  420. if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
  421. regmap_field_update_bits(scodec->reg_adc_fifoc,
  422. BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS),
  423. BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
  424. regmap_field_update_bits(scodec->reg_adc_fifoc,
  425. BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
  426. 0);
  427. scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  428. } else {
  429. regmap_field_update_bits(scodec->reg_adc_fifoc,
  430. BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS),
  431. 0);
  432. /* Fill most significant bits with valid data MSB */
  433. regmap_field_update_bits(scodec->reg_adc_fifoc,
  434. BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
  435. BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
  436. scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  437. }
  438. return 0;
  439. }
  440. static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
  441. struct snd_pcm_hw_params *params,
  442. unsigned int hwrate)
  443. {
  444. u32 val;
  445. /* Set DAC sample rate */
  446. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  447. 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
  448. hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
  449. /* Set the number of channels we want to use */
  450. if (params_channels(params) == 1)
  451. val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
  452. else
  453. val = 0;
  454. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  455. BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
  456. val);
  457. /* Set the number of sample bits to either 16 or 24 bits */
  458. if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
  459. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  460. BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
  461. BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
  462. /* Set TX FIFO mode to padding the LSBs with 0 */
  463. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  464. BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
  465. 0);
  466. scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  467. } else {
  468. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  469. BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
  470. 0);
  471. /* Set TX FIFO mode to repeat the MSB */
  472. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  473. BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
  474. BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
  475. scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  476. }
  477. return 0;
  478. }
  479. static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
  480. struct snd_pcm_hw_params *params,
  481. struct snd_soc_dai *dai)
  482. {
  483. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  484. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
  485. unsigned long clk_freq;
  486. int ret, hwrate;
  487. clk_freq = sun4i_codec_get_mod_freq(params);
  488. if (!clk_freq)
  489. return -EINVAL;
  490. ret = clk_set_rate(scodec->clk_module, clk_freq);
  491. if (ret)
  492. return ret;
  493. hwrate = sun4i_codec_get_hw_rate(params);
  494. if (hwrate < 0)
  495. return hwrate;
  496. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  497. return sun4i_codec_hw_params_playback(scodec, params,
  498. hwrate);
  499. return sun4i_codec_hw_params_capture(scodec, params,
  500. hwrate);
  501. }
  502. static unsigned int sun4i_codec_src_rates[] = {
  503. 8000, 11025, 12000, 16000, 22050, 24000, 32000,
  504. 44100, 48000, 96000, 192000
  505. };
  506. static struct snd_pcm_hw_constraint_list sun4i_codec_constraints = {
  507. .count = ARRAY_SIZE(sun4i_codec_src_rates),
  508. .list = sun4i_codec_src_rates,
  509. };
  510. static int sun4i_codec_startup(struct snd_pcm_substream *substream,
  511. struct snd_soc_dai *dai)
  512. {
  513. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  514. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
  515. snd_pcm_hw_constraint_list(substream->runtime, 0,
  516. SNDRV_PCM_HW_PARAM_RATE, &sun4i_codec_constraints);
  517. /*
  518. * Stop issuing DRQ when we have room for less than 16 samples
  519. * in our TX FIFO
  520. */
  521. regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
  522. 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT,
  523. 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
  524. return clk_prepare_enable(scodec->clk_module);
  525. }
  526. static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
  527. struct snd_soc_dai *dai)
  528. {
  529. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  530. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
  531. clk_disable_unprepare(scodec->clk_module);
  532. }
  533. static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
  534. .startup = sun4i_codec_startup,
  535. .shutdown = sun4i_codec_shutdown,
  536. .trigger = sun4i_codec_trigger,
  537. .hw_params = sun4i_codec_hw_params,
  538. .prepare = sun4i_codec_prepare,
  539. };
  540. static struct snd_soc_dai_driver sun4i_codec_dai = {
  541. .name = "Codec",
  542. .ops = &sun4i_codec_dai_ops,
  543. .playback = {
  544. .stream_name = "Codec Playback",
  545. .channels_min = 1,
  546. .channels_max = 2,
  547. .rate_min = 8000,
  548. .rate_max = 192000,
  549. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  550. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  551. SNDRV_PCM_FMTBIT_S32_LE,
  552. .sig_bits = 24,
  553. },
  554. .capture = {
  555. .stream_name = "Codec Capture",
  556. .channels_min = 1,
  557. .channels_max = 2,
  558. .rate_min = 8000,
  559. .rate_max = 48000,
  560. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  561. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  562. SNDRV_PCM_FMTBIT_S32_LE,
  563. .sig_bits = 24,
  564. },
  565. };
  566. /*** sun4i Codec ***/
  567. static const struct snd_kcontrol_new sun4i_codec_pa_mute =
  568. SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
  569. SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
  570. static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
  571. static const struct snd_kcontrol_new sun4i_codec_controls[] = {
  572. SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
  573. SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
  574. sun4i_codec_pa_volume_scale),
  575. };
  576. static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[] = {
  577. SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
  578. SUN4I_CODEC_DAC_ACTL_LDACLMIXS, 1, 0),
  579. };
  580. static const struct snd_kcontrol_new sun4i_codec_right_mixer_controls[] = {
  581. SOC_DAPM_SINGLE("Right DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
  582. SUN4I_CODEC_DAC_ACTL_RDACRMIXS, 1, 0),
  583. SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
  584. SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
  585. };
  586. static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
  587. SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
  588. SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
  589. SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
  590. SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
  591. };
  592. static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
  593. /* Digital parts of the ADCs */
  594. SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC,
  595. SUN4I_CODEC_ADC_FIFOC_EN_AD, 0,
  596. NULL, 0),
  597. /* Digital parts of the DACs */
  598. SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
  599. SUN4I_CODEC_DAC_DPC_EN_DA, 0,
  600. NULL, 0),
  601. /* Analog parts of the ADCs */
  602. SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
  603. SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0),
  604. SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
  605. SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0),
  606. /* Analog parts of the DACs */
  607. SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
  608. SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
  609. SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
  610. SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
  611. /* Mixers */
  612. SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
  613. sun4i_codec_left_mixer_controls,
  614. ARRAY_SIZE(sun4i_codec_left_mixer_controls)),
  615. SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
  616. sun4i_codec_right_mixer_controls,
  617. ARRAY_SIZE(sun4i_codec_right_mixer_controls)),
  618. /* Global Mixer Enable */
  619. SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
  620. SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
  621. /* VMIC */
  622. SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL,
  623. SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0),
  624. /* Mic Pre-Amplifiers */
  625. SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
  626. SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0),
  627. /* Power Amplifier */
  628. SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
  629. SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
  630. sun4i_codec_pa_mixer_controls,
  631. ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
  632. SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0,
  633. &sun4i_codec_pa_mute),
  634. SND_SOC_DAPM_INPUT("Mic1"),
  635. SND_SOC_DAPM_OUTPUT("HP Right"),
  636. SND_SOC_DAPM_OUTPUT("HP Left"),
  637. };
  638. static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
  639. /* Left ADC / DAC Routes */
  640. { "Left ADC", NULL, "ADC" },
  641. { "Left DAC", NULL, "DAC" },
  642. /* Right ADC / DAC Routes */
  643. { "Right ADC", NULL, "ADC" },
  644. { "Right DAC", NULL, "DAC" },
  645. /* Right Mixer Routes */
  646. { "Right Mixer", NULL, "Mixer Enable" },
  647. { "Right Mixer", "Left DAC Playback Switch", "Left DAC" },
  648. { "Right Mixer", "Right DAC Playback Switch", "Right DAC" },
  649. /* Left Mixer Routes */
  650. { "Left Mixer", NULL, "Mixer Enable" },
  651. { "Left Mixer", "Left DAC Playback Switch", "Left DAC" },
  652. /* Power Amplifier Routes */
  653. { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" },
  654. { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" },
  655. { "Power Amplifier", "DAC Playback Switch", "Left DAC" },
  656. { "Power Amplifier", "DAC Playback Switch", "Right DAC" },
  657. /* Headphone Output Routes */
  658. { "Power Amplifier Mute", "Switch", "Power Amplifier" },
  659. { "HP Right", NULL, "Power Amplifier Mute" },
  660. { "HP Left", NULL, "Power Amplifier Mute" },
  661. /* Mic1 Routes */
  662. { "Left ADC", NULL, "MIC1 Pre-Amplifier" },
  663. { "Right ADC", NULL, "MIC1 Pre-Amplifier" },
  664. { "MIC1 Pre-Amplifier", NULL, "Mic1"},
  665. { "Mic1", NULL, "VMIC" },
  666. };
  667. static const struct snd_soc_component_driver sun4i_codec_codec = {
  668. .controls = sun4i_codec_controls,
  669. .num_controls = ARRAY_SIZE(sun4i_codec_controls),
  670. .dapm_widgets = sun4i_codec_codec_dapm_widgets,
  671. .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
  672. .dapm_routes = sun4i_codec_codec_dapm_routes,
  673. .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
  674. .idle_bias_on = 1,
  675. .use_pmdown_time = 1,
  676. .endianness = 1,
  677. .non_legacy_dai_naming = 1,
  678. };
  679. /*** sun6i Codec ***/
  680. /* mixer controls */
  681. static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
  682. SOC_DAPM_DOUBLE("DAC Playback Switch",
  683. SUN6I_CODEC_OM_DACA_CTRL,
  684. SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL,
  685. SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0),
  686. SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
  687. SUN6I_CODEC_OM_DACA_CTRL,
  688. SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR,
  689. SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0),
  690. SOC_DAPM_DOUBLE("Line In Playback Switch",
  691. SUN6I_CODEC_OM_DACA_CTRL,
  692. SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL,
  693. SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0),
  694. SOC_DAPM_DOUBLE("Mic1 Playback Switch",
  695. SUN6I_CODEC_OM_DACA_CTRL,
  696. SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1,
  697. SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0),
  698. SOC_DAPM_DOUBLE("Mic2 Playback Switch",
  699. SUN6I_CODEC_OM_DACA_CTRL,
  700. SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2,
  701. SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0),
  702. };
  703. /* ADC mixer controls */
  704. static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = {
  705. SOC_DAPM_DOUBLE("Mixer Capture Switch",
  706. SUN6I_CODEC_ADC_ACTL,
  707. SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL,
  708. SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0),
  709. SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
  710. SUN6I_CODEC_ADC_ACTL,
  711. SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR,
  712. SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0),
  713. SOC_DAPM_DOUBLE("Line In Capture Switch",
  714. SUN6I_CODEC_ADC_ACTL,
  715. SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL,
  716. SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0),
  717. SOC_DAPM_DOUBLE("Mic1 Capture Switch",
  718. SUN6I_CODEC_ADC_ACTL,
  719. SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1,
  720. SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0),
  721. SOC_DAPM_DOUBLE("Mic2 Capture Switch",
  722. SUN6I_CODEC_ADC_ACTL,
  723. SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2,
  724. SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0),
  725. };
  726. /* headphone controls */
  727. static const char * const sun6i_codec_hp_src_enum_text[] = {
  728. "DAC", "Mixer",
  729. };
  730. static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
  731. SUN6I_CODEC_OM_DACA_CTRL,
  732. SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
  733. SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
  734. sun6i_codec_hp_src_enum_text);
  735. static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
  736. SOC_DAPM_ENUM("Headphone Source Playback Route",
  737. sun6i_codec_hp_src_enum),
  738. };
  739. /* microphone controls */
  740. static const char * const sun6i_codec_mic2_src_enum_text[] = {
  741. "Mic2", "Mic3",
  742. };
  743. static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum,
  744. SUN6I_CODEC_MIC_CTRL,
  745. SUN6I_CODEC_MIC_CTRL_MIC2SLT,
  746. sun6i_codec_mic2_src_enum_text);
  747. static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = {
  748. SOC_DAPM_ENUM("Mic2 Amplifier Source Route",
  749. sun6i_codec_mic2_src_enum),
  750. };
  751. /* line out controls */
  752. static const char * const sun6i_codec_lineout_src_enum_text[] = {
  753. "Stereo", "Mono Differential",
  754. };
  755. static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum,
  756. SUN6I_CODEC_MIC_CTRL,
  757. SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC,
  758. SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC,
  759. sun6i_codec_lineout_src_enum_text);
  760. static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = {
  761. SOC_DAPM_ENUM("Line Out Source Playback Route",
  762. sun6i_codec_lineout_src_enum),
  763. };
  764. /* volume / mute controls */
  765. static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0);
  766. static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1);
  767. static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale,
  768. -450, 150, 0);
  769. static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale,
  770. 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
  771. 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
  772. );
  773. static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale,
  774. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  775. 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
  776. );
  777. static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
  778. SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
  779. SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
  780. sun6i_codec_dvol_scale),
  781. SOC_SINGLE_TLV("Headphone Playback Volume",
  782. SUN6I_CODEC_OM_DACA_CTRL,
  783. SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0,
  784. sun6i_codec_hp_vol_scale),
  785. SOC_SINGLE_TLV("Line Out Playback Volume",
  786. SUN6I_CODEC_MIC_CTRL,
  787. SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0,
  788. sun6i_codec_lineout_vol_scale),
  789. SOC_DOUBLE("Headphone Playback Switch",
  790. SUN6I_CODEC_OM_DACA_CTRL,
  791. SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE,
  792. SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0),
  793. SOC_DOUBLE("Line Out Playback Switch",
  794. SUN6I_CODEC_MIC_CTRL,
  795. SUN6I_CODEC_MIC_CTRL_LINEOUTLEN,
  796. SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0),
  797. /* Mixer pre-gains */
  798. SOC_SINGLE_TLV("Line In Playback Volume",
  799. SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING,
  800. 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
  801. SOC_SINGLE_TLV("Mic1 Playback Volume",
  802. SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G,
  803. 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
  804. SOC_SINGLE_TLV("Mic2 Playback Volume",
  805. SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G,
  806. 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
  807. /* Microphone Amp boost gains */
  808. SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL,
  809. SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0,
  810. sun6i_codec_mic_gain_scale),
  811. SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL,
  812. SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0,
  813. sun6i_codec_mic_gain_scale),
  814. SOC_DOUBLE_TLV("ADC Capture Volume",
  815. SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG,
  816. SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0,
  817. sun6i_codec_out_mixer_pregain_scale),
  818. };
  819. static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
  820. /* Microphone inputs */
  821. SND_SOC_DAPM_INPUT("MIC1"),
  822. SND_SOC_DAPM_INPUT("MIC2"),
  823. SND_SOC_DAPM_INPUT("MIC3"),
  824. /* Microphone Bias */
  825. SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL,
  826. SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0),
  827. SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL,
  828. SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0),
  829. /* Mic input path */
  830. SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route",
  831. SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src),
  832. SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL,
  833. SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0),
  834. SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL,
  835. SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0),
  836. /* Line In */
  837. SND_SOC_DAPM_INPUT("LINEIN"),
  838. /* Digital parts of the ADCs */
  839. SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
  840. SUN6I_CODEC_ADC_FIFOC_EN_AD, 0,
  841. NULL, 0),
  842. /* Analog parts of the ADCs */
  843. SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
  844. SUN6I_CODEC_ADC_ACTL_ADCLEN, 0),
  845. SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
  846. SUN6I_CODEC_ADC_ACTL_ADCREN, 0),
  847. /* ADC Mixers */
  848. SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
  849. sun6i_codec_adc_mixer_controls),
  850. SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
  851. sun6i_codec_adc_mixer_controls),
  852. /* Digital parts of the DACs */
  853. SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
  854. SUN4I_CODEC_DAC_DPC_EN_DA, 0,
  855. NULL, 0),
  856. /* Analog parts of the DACs */
  857. SND_SOC_DAPM_DAC("Left DAC", "Codec Playback",
  858. SUN6I_CODEC_OM_DACA_CTRL,
  859. SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0),
  860. SND_SOC_DAPM_DAC("Right DAC", "Codec Playback",
  861. SUN6I_CODEC_OM_DACA_CTRL,
  862. SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0),
  863. /* Mixers */
  864. SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL,
  865. SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0,
  866. sun6i_codec_mixer_controls),
  867. SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL,
  868. SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0,
  869. sun6i_codec_mixer_controls),
  870. /* Headphone output path */
  871. SND_SOC_DAPM_MUX("Headphone Source Playback Route",
  872. SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
  873. SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL,
  874. SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0),
  875. SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL,
  876. SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0),
  877. SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL,
  878. SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0),
  879. SND_SOC_DAPM_OUTPUT("HP"),
  880. /* Line Out path */
  881. SND_SOC_DAPM_MUX("Line Out Source Playback Route",
  882. SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src),
  883. SND_SOC_DAPM_OUTPUT("LINEOUT"),
  884. };
  885. static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
  886. /* DAC Routes */
  887. { "Left DAC", NULL, "DAC Enable" },
  888. { "Right DAC", NULL, "DAC Enable" },
  889. /* Microphone Routes */
  890. { "Mic1 Amplifier", NULL, "MIC1"},
  891. { "Mic2 Amplifier Source Route", "Mic2", "MIC2" },
  892. { "Mic2 Amplifier Source Route", "Mic3", "MIC3" },
  893. { "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"},
  894. /* Left Mixer Routes */
  895. { "Left Mixer", "DAC Playback Switch", "Left DAC" },
  896. { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
  897. { "Left Mixer", "Line In Playback Switch", "LINEIN" },
  898. { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
  899. { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
  900. /* Right Mixer Routes */
  901. { "Right Mixer", "DAC Playback Switch", "Right DAC" },
  902. { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
  903. { "Right Mixer", "Line In Playback Switch", "LINEIN" },
  904. { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
  905. { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
  906. /* Left ADC Mixer Routes */
  907. { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
  908. { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
  909. { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
  910. { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
  911. { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
  912. /* Right ADC Mixer Routes */
  913. { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
  914. { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
  915. { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
  916. { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
  917. { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
  918. /* Headphone Routes */
  919. { "Headphone Source Playback Route", "DAC", "Left DAC" },
  920. { "Headphone Source Playback Route", "DAC", "Right DAC" },
  921. { "Headphone Source Playback Route", "Mixer", "Left Mixer" },
  922. { "Headphone Source Playback Route", "Mixer", "Right Mixer" },
  923. { "Headphone Amp", NULL, "Headphone Source Playback Route" },
  924. { "HP", NULL, "Headphone Amp" },
  925. { "HPCOM", NULL, "HPCOM Protection" },
  926. /* Line Out Routes */
  927. { "Line Out Source Playback Route", "Stereo", "Left Mixer" },
  928. { "Line Out Source Playback Route", "Stereo", "Right Mixer" },
  929. { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
  930. { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
  931. { "LINEOUT", NULL, "Line Out Source Playback Route" },
  932. /* ADC Routes */
  933. { "Left ADC", NULL, "ADC Enable" },
  934. { "Right ADC", NULL, "ADC Enable" },
  935. { "Left ADC", NULL, "Left ADC Mixer" },
  936. { "Right ADC", NULL, "Right ADC Mixer" },
  937. };
  938. static const struct snd_soc_component_driver sun6i_codec_codec = {
  939. .controls = sun6i_codec_codec_widgets,
  940. .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets),
  941. .dapm_widgets = sun6i_codec_codec_dapm_widgets,
  942. .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets),
  943. .dapm_routes = sun6i_codec_codec_dapm_routes,
  944. .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes),
  945. .idle_bias_on = 1,
  946. .use_pmdown_time = 1,
  947. .endianness = 1,
  948. .non_legacy_dai_naming = 1,
  949. };
  950. /* sun8i A23 codec */
  951. static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = {
  952. SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
  953. SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
  954. sun6i_codec_dvol_scale),
  955. };
  956. static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = {
  957. /* Digital parts of the ADCs */
  958. SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
  959. SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
  960. /* Digital parts of the DACs */
  961. SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
  962. SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
  963. };
  964. static const struct snd_soc_component_driver sun8i_a23_codec_codec = {
  965. .controls = sun8i_a23_codec_codec_controls,
  966. .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls),
  967. .dapm_widgets = sun8i_a23_codec_codec_widgets,
  968. .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets),
  969. .idle_bias_on = 1,
  970. .use_pmdown_time = 1,
  971. .endianness = 1,
  972. .non_legacy_dai_naming = 1,
  973. };
  974. static const struct snd_soc_component_driver sun4i_codec_component = {
  975. .name = "sun4i-codec",
  976. };
  977. #define SUN4I_CODEC_RATES SNDRV_PCM_RATE_CONTINUOUS
  978. #define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  979. SNDRV_PCM_FMTBIT_S32_LE)
  980. static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
  981. {
  982. struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
  983. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
  984. snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
  985. &scodec->capture_dma_data);
  986. return 0;
  987. }
  988. static struct snd_soc_dai_driver dummy_cpu_dai = {
  989. .name = "sun4i-codec-cpu-dai",
  990. .probe = sun4i_codec_dai_probe,
  991. .playback = {
  992. .stream_name = "Playback",
  993. .channels_min = 1,
  994. .channels_max = 2,
  995. .rates = SUN4I_CODEC_RATES,
  996. .formats = SUN4I_CODEC_FORMATS,
  997. .sig_bits = 24,
  998. },
  999. .capture = {
  1000. .stream_name = "Capture",
  1001. .channels_min = 1,
  1002. .channels_max = 2,
  1003. .rates = SUN4I_CODEC_RATES,
  1004. .formats = SUN4I_CODEC_FORMATS,
  1005. .sig_bits = 24,
  1006. },
  1007. };
  1008. static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
  1009. int *num_links)
  1010. {
  1011. struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
  1012. GFP_KERNEL);
  1013. if (!link)
  1014. return NULL;
  1015. link->name = "cdc";
  1016. link->stream_name = "CDC PCM";
  1017. link->codec_dai_name = "Codec";
  1018. link->cpu_dai_name = dev_name(dev);
  1019. link->codec_name = dev_name(dev);
  1020. link->platform_name = dev_name(dev);
  1021. link->dai_fmt = SND_SOC_DAIFMT_I2S;
  1022. *num_links = 1;
  1023. return link;
  1024. };
  1025. static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w,
  1026. struct snd_kcontrol *k, int event)
  1027. {
  1028. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
  1029. gpiod_set_value_cansleep(scodec->gpio_pa,
  1030. !!SND_SOC_DAPM_EVENT_ON(event));
  1031. return 0;
  1032. }
  1033. static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = {
  1034. SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
  1035. };
  1036. static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = {
  1037. { "Speaker", NULL, "HP Right" },
  1038. { "Speaker", NULL, "HP Left" },
  1039. };
  1040. static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
  1041. {
  1042. struct snd_soc_card *card;
  1043. card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
  1044. if (!card)
  1045. return ERR_PTR(-ENOMEM);
  1046. card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
  1047. if (!card->dai_link)
  1048. return ERR_PTR(-ENOMEM);
  1049. card->dev = dev;
  1050. card->owner = THIS_MODULE;
  1051. card->name = "sun4i-codec";
  1052. card->dapm_widgets = sun4i_codec_card_dapm_widgets;
  1053. card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets);
  1054. card->dapm_routes = sun4i_codec_card_dapm_routes;
  1055. card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes);
  1056. return card;
  1057. };
  1058. static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
  1059. SND_SOC_DAPM_HP("Headphone", NULL),
  1060. SND_SOC_DAPM_LINE("Line In", NULL),
  1061. SND_SOC_DAPM_LINE("Line Out", NULL),
  1062. SND_SOC_DAPM_MIC("Headset Mic", NULL),
  1063. SND_SOC_DAPM_MIC("Mic", NULL),
  1064. SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
  1065. };
  1066. static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
  1067. {
  1068. struct snd_soc_card *card;
  1069. int ret;
  1070. card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
  1071. if (!card)
  1072. return ERR_PTR(-ENOMEM);
  1073. card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
  1074. if (!card->dai_link)
  1075. return ERR_PTR(-ENOMEM);
  1076. card->dev = dev;
  1077. card->owner = THIS_MODULE;
  1078. card->name = "A31 Audio Codec";
  1079. card->dapm_widgets = sun6i_codec_card_dapm_widgets;
  1080. card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
  1081. card->fully_routed = true;
  1082. ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
  1083. if (ret)
  1084. dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
  1085. return card;
  1086. };
  1087. /* Connect digital side enables to analog side widgets */
  1088. static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
  1089. /* ADC Routes */
  1090. { "Left ADC", NULL, "ADC Enable" },
  1091. { "Right ADC", NULL, "ADC Enable" },
  1092. { "Codec Capture", NULL, "Left ADC" },
  1093. { "Codec Capture", NULL, "Right ADC" },
  1094. /* DAC Routes */
  1095. { "Left DAC", NULL, "DAC Enable" },
  1096. { "Right DAC", NULL, "DAC Enable" },
  1097. { "Left DAC", NULL, "Codec Playback" },
  1098. { "Right DAC", NULL, "Codec Playback" },
  1099. };
  1100. static struct snd_soc_aux_dev aux_dev = {
  1101. .name = "Codec Analog Controls",
  1102. };
  1103. static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
  1104. {
  1105. struct snd_soc_card *card;
  1106. int ret;
  1107. card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
  1108. if (!card)
  1109. return ERR_PTR(-ENOMEM);
  1110. aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
  1111. "allwinner,codec-analog-controls",
  1112. 0);
  1113. if (!aux_dev.codec_of_node) {
  1114. dev_err(dev, "Can't find analog controls for codec.\n");
  1115. return ERR_PTR(-EINVAL);
  1116. };
  1117. card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
  1118. if (!card->dai_link)
  1119. return ERR_PTR(-ENOMEM);
  1120. card->dev = dev;
  1121. card->owner = THIS_MODULE;
  1122. card->name = "A23 Audio Codec";
  1123. card->dapm_widgets = sun6i_codec_card_dapm_widgets;
  1124. card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
  1125. card->dapm_routes = sun8i_codec_card_routes;
  1126. card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
  1127. card->aux_dev = &aux_dev;
  1128. card->num_aux_devs = 1;
  1129. card->fully_routed = true;
  1130. ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
  1131. if (ret)
  1132. dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
  1133. return card;
  1134. };
  1135. static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev)
  1136. {
  1137. struct snd_soc_card *card;
  1138. int ret;
  1139. card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
  1140. if (!card)
  1141. return ERR_PTR(-ENOMEM);
  1142. aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
  1143. "allwinner,codec-analog-controls",
  1144. 0);
  1145. if (!aux_dev.codec_of_node) {
  1146. dev_err(dev, "Can't find analog controls for codec.\n");
  1147. return ERR_PTR(-EINVAL);
  1148. };
  1149. card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
  1150. if (!card->dai_link)
  1151. return ERR_PTR(-ENOMEM);
  1152. card->dev = dev;
  1153. card->owner = THIS_MODULE;
  1154. card->name = "H3 Audio Codec";
  1155. card->dapm_widgets = sun6i_codec_card_dapm_widgets;
  1156. card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
  1157. card->dapm_routes = sun8i_codec_card_routes;
  1158. card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
  1159. card->aux_dev = &aux_dev;
  1160. card->num_aux_devs = 1;
  1161. card->fully_routed = true;
  1162. ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
  1163. if (ret)
  1164. dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
  1165. return card;
  1166. };
  1167. static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev)
  1168. {
  1169. struct snd_soc_card *card;
  1170. int ret;
  1171. card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
  1172. if (!card)
  1173. return ERR_PTR(-ENOMEM);
  1174. aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
  1175. "allwinner,codec-analog-controls",
  1176. 0);
  1177. if (!aux_dev.codec_of_node) {
  1178. dev_err(dev, "Can't find analog controls for codec.\n");
  1179. return ERR_PTR(-EINVAL);
  1180. };
  1181. card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
  1182. if (!card->dai_link)
  1183. return ERR_PTR(-ENOMEM);
  1184. card->dev = dev;
  1185. card->owner = THIS_MODULE;
  1186. card->name = "V3s Audio Codec";
  1187. card->dapm_widgets = sun6i_codec_card_dapm_widgets;
  1188. card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
  1189. card->dapm_routes = sun8i_codec_card_routes;
  1190. card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
  1191. card->aux_dev = &aux_dev;
  1192. card->num_aux_devs = 1;
  1193. card->fully_routed = true;
  1194. ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
  1195. if (ret)
  1196. dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
  1197. return card;
  1198. };
  1199. static const struct regmap_config sun4i_codec_regmap_config = {
  1200. .reg_bits = 32,
  1201. .reg_stride = 4,
  1202. .val_bits = 32,
  1203. .max_register = SUN4I_CODEC_ADC_RXCNT,
  1204. };
  1205. static const struct regmap_config sun6i_codec_regmap_config = {
  1206. .reg_bits = 32,
  1207. .reg_stride = 4,
  1208. .val_bits = 32,
  1209. .max_register = SUN6I_CODEC_HMIC_DATA,
  1210. };
  1211. static const struct regmap_config sun7i_codec_regmap_config = {
  1212. .reg_bits = 32,
  1213. .reg_stride = 4,
  1214. .val_bits = 32,
  1215. .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
  1216. };
  1217. static const struct regmap_config sun8i_a23_codec_regmap_config = {
  1218. .reg_bits = 32,
  1219. .reg_stride = 4,
  1220. .val_bits = 32,
  1221. .max_register = SUN8I_A23_CODEC_ADC_RXCNT,
  1222. };
  1223. static const struct regmap_config sun8i_h3_codec_regmap_config = {
  1224. .reg_bits = 32,
  1225. .reg_stride = 4,
  1226. .val_bits = 32,
  1227. .max_register = SUN8I_H3_CODEC_ADC_DBG,
  1228. };
  1229. static const struct regmap_config sun8i_v3s_codec_regmap_config = {
  1230. .reg_bits = 32,
  1231. .reg_stride = 4,
  1232. .val_bits = 32,
  1233. .max_register = SUN8I_H3_CODEC_ADC_DBG,
  1234. };
  1235. struct sun4i_codec_quirks {
  1236. const struct regmap_config *regmap_config;
  1237. const struct snd_soc_component_driver *codec;
  1238. struct snd_soc_card * (*create_card)(struct device *dev);
  1239. struct reg_field reg_adc_fifoc; /* used for regmap_field */
  1240. unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
  1241. unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
  1242. bool has_reset;
  1243. };
  1244. static const struct sun4i_codec_quirks sun4i_codec_quirks = {
  1245. .regmap_config = &sun4i_codec_regmap_config,
  1246. .codec = &sun4i_codec_codec,
  1247. .create_card = sun4i_codec_create_card,
  1248. .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
  1249. .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
  1250. .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
  1251. };
  1252. static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
  1253. .regmap_config = &sun6i_codec_regmap_config,
  1254. .codec = &sun6i_codec_codec,
  1255. .create_card = sun6i_codec_create_card,
  1256. .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
  1257. .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
  1258. .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
  1259. .has_reset = true,
  1260. };
  1261. static const struct sun4i_codec_quirks sun7i_codec_quirks = {
  1262. .regmap_config = &sun7i_codec_regmap_config,
  1263. .codec = &sun4i_codec_codec,
  1264. .create_card = sun4i_codec_create_card,
  1265. .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
  1266. .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
  1267. .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
  1268. };
  1269. static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
  1270. .regmap_config = &sun8i_a23_codec_regmap_config,
  1271. .codec = &sun8i_a23_codec_codec,
  1272. .create_card = sun8i_a23_codec_create_card,
  1273. .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
  1274. .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
  1275. .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
  1276. .has_reset = true,
  1277. };
  1278. static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
  1279. .regmap_config = &sun8i_h3_codec_regmap_config,
  1280. /*
  1281. * TODO Share the codec structure with A23 for now.
  1282. * This should be split out when adding digital audio
  1283. * processing support for the H3.
  1284. */
  1285. .codec = &sun8i_a23_codec_codec,
  1286. .create_card = sun8i_h3_codec_create_card,
  1287. .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
  1288. .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
  1289. .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
  1290. .has_reset = true,
  1291. };
  1292. static const struct sun4i_codec_quirks sun8i_v3s_codec_quirks = {
  1293. .regmap_config = &sun8i_v3s_codec_regmap_config,
  1294. /*
  1295. * TODO The codec structure should be split out, like
  1296. * H3, when adding digital audio processing support.
  1297. */
  1298. .codec = &sun8i_a23_codec_codec,
  1299. .create_card = sun8i_v3s_codec_create_card,
  1300. .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
  1301. .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
  1302. .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
  1303. .has_reset = true,
  1304. };
  1305. static const struct of_device_id sun4i_codec_of_match[] = {
  1306. {
  1307. .compatible = "allwinner,sun4i-a10-codec",
  1308. .data = &sun4i_codec_quirks,
  1309. },
  1310. {
  1311. .compatible = "allwinner,sun6i-a31-codec",
  1312. .data = &sun6i_a31_codec_quirks,
  1313. },
  1314. {
  1315. .compatible = "allwinner,sun7i-a20-codec",
  1316. .data = &sun7i_codec_quirks,
  1317. },
  1318. {
  1319. .compatible = "allwinner,sun8i-a23-codec",
  1320. .data = &sun8i_a23_codec_quirks,
  1321. },
  1322. {
  1323. .compatible = "allwinner,sun8i-h3-codec",
  1324. .data = &sun8i_h3_codec_quirks,
  1325. },
  1326. {
  1327. .compatible = "allwinner,sun8i-v3s-codec",
  1328. .data = &sun8i_v3s_codec_quirks,
  1329. },
  1330. {}
  1331. };
  1332. MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
  1333. static int sun4i_codec_probe(struct platform_device *pdev)
  1334. {
  1335. struct snd_soc_card *card;
  1336. struct sun4i_codec *scodec;
  1337. const struct sun4i_codec_quirks *quirks;
  1338. struct resource *res;
  1339. void __iomem *base;
  1340. int ret;
  1341. scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
  1342. if (!scodec)
  1343. return -ENOMEM;
  1344. scodec->dev = &pdev->dev;
  1345. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1346. base = devm_ioremap_resource(&pdev->dev, res);
  1347. if (IS_ERR(base)) {
  1348. dev_err(&pdev->dev, "Failed to map the registers\n");
  1349. return PTR_ERR(base);
  1350. }
  1351. quirks = of_device_get_match_data(&pdev->dev);
  1352. if (quirks == NULL) {
  1353. dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
  1354. return -ENODEV;
  1355. }
  1356. scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
  1357. quirks->regmap_config);
  1358. if (IS_ERR(scodec->regmap)) {
  1359. dev_err(&pdev->dev, "Failed to create our regmap\n");
  1360. return PTR_ERR(scodec->regmap);
  1361. }
  1362. /* Get the clocks from the DT */
  1363. scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
  1364. if (IS_ERR(scodec->clk_apb)) {
  1365. dev_err(&pdev->dev, "Failed to get the APB clock\n");
  1366. return PTR_ERR(scodec->clk_apb);
  1367. }
  1368. scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
  1369. if (IS_ERR(scodec->clk_module)) {
  1370. dev_err(&pdev->dev, "Failed to get the module clock\n");
  1371. return PTR_ERR(scodec->clk_module);
  1372. }
  1373. if (quirks->has_reset) {
  1374. scodec->rst = devm_reset_control_get_exclusive(&pdev->dev,
  1375. NULL);
  1376. if (IS_ERR(scodec->rst)) {
  1377. dev_err(&pdev->dev, "Failed to get reset control\n");
  1378. return PTR_ERR(scodec->rst);
  1379. }
  1380. }
  1381. scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
  1382. GPIOD_OUT_LOW);
  1383. if (IS_ERR(scodec->gpio_pa)) {
  1384. ret = PTR_ERR(scodec->gpio_pa);
  1385. if (ret != -EPROBE_DEFER)
  1386. dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret);
  1387. return ret;
  1388. }
  1389. /* reg_field setup */
  1390. scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev,
  1391. scodec->regmap,
  1392. quirks->reg_adc_fifoc);
  1393. if (IS_ERR(scodec->reg_adc_fifoc)) {
  1394. ret = PTR_ERR(scodec->reg_adc_fifoc);
  1395. dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
  1396. ret);
  1397. return ret;
  1398. }
  1399. /* Enable the bus clock */
  1400. if (clk_prepare_enable(scodec->clk_apb)) {
  1401. dev_err(&pdev->dev, "Failed to enable the APB clock\n");
  1402. return -EINVAL;
  1403. }
  1404. /* Deassert the reset control */
  1405. if (scodec->rst) {
  1406. ret = reset_control_deassert(scodec->rst);
  1407. if (ret) {
  1408. dev_err(&pdev->dev,
  1409. "Failed to deassert the reset control\n");
  1410. goto err_clk_disable;
  1411. }
  1412. }
  1413. /* DMA configuration for TX FIFO */
  1414. scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
  1415. scodec->playback_dma_data.maxburst = 8;
  1416. scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  1417. /* DMA configuration for RX FIFO */
  1418. scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata;
  1419. scodec->capture_dma_data.maxburst = 8;
  1420. scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  1421. ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec,
  1422. &sun4i_codec_dai, 1);
  1423. if (ret) {
  1424. dev_err(&pdev->dev, "Failed to register our codec\n");
  1425. goto err_assert_reset;
  1426. }
  1427. ret = devm_snd_soc_register_component(&pdev->dev,
  1428. &sun4i_codec_component,
  1429. &dummy_cpu_dai, 1);
  1430. if (ret) {
  1431. dev_err(&pdev->dev, "Failed to register our DAI\n");
  1432. goto err_assert_reset;
  1433. }
  1434. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  1435. if (ret) {
  1436. dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
  1437. goto err_assert_reset;
  1438. }
  1439. card = quirks->create_card(&pdev->dev);
  1440. if (IS_ERR(card)) {
  1441. ret = PTR_ERR(card);
  1442. dev_err(&pdev->dev, "Failed to create our card\n");
  1443. goto err_assert_reset;
  1444. }
  1445. snd_soc_card_set_drvdata(card, scodec);
  1446. ret = snd_soc_register_card(card);
  1447. if (ret) {
  1448. dev_err(&pdev->dev, "Failed to register our card\n");
  1449. goto err_assert_reset;
  1450. }
  1451. return 0;
  1452. err_assert_reset:
  1453. if (scodec->rst)
  1454. reset_control_assert(scodec->rst);
  1455. err_clk_disable:
  1456. clk_disable_unprepare(scodec->clk_apb);
  1457. return ret;
  1458. }
  1459. static int sun4i_codec_remove(struct platform_device *pdev)
  1460. {
  1461. struct snd_soc_card *card = platform_get_drvdata(pdev);
  1462. struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
  1463. snd_soc_unregister_card(card);
  1464. if (scodec->rst)
  1465. reset_control_assert(scodec->rst);
  1466. clk_disable_unprepare(scodec->clk_apb);
  1467. return 0;
  1468. }
  1469. static struct platform_driver sun4i_codec_driver = {
  1470. .driver = {
  1471. .name = "sun4i-codec",
  1472. .of_match_table = sun4i_codec_of_match,
  1473. },
  1474. .probe = sun4i_codec_probe,
  1475. .remove = sun4i_codec_remove,
  1476. };
  1477. module_platform_driver(sun4i_codec_driver);
  1478. MODULE_DESCRIPTION("Allwinner A10 codec driver");
  1479. MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
  1480. MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
  1481. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  1482. MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
  1483. MODULE_LICENSE("GPL");