aio-cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Socionext UniPhier AIO ALSA CPU DAI driver.
  4. //
  5. // Copyright (c) 2016-2018 Socionext Inc.
  6. #include <linux/clk.h>
  7. #include <linux/errno.h>
  8. #include <linux/kernel.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/reset.h>
  15. #include <sound/core.h>
  16. #include <sound/pcm.h>
  17. #include <sound/pcm_params.h>
  18. #include <sound/soc.h>
  19. #include "aio.h"
  20. static bool is_valid_pll(struct uniphier_aio_chip *chip, int pll_id)
  21. {
  22. struct device *dev = &chip->pdev->dev;
  23. if (pll_id < 0 || chip->num_plls <= pll_id) {
  24. dev_err(dev, "PLL(%d) is not supported\n", pll_id);
  25. return false;
  26. }
  27. return chip->plls[pll_id].enable;
  28. }
  29. /**
  30. * find_volume - find volume supported HW port by HW port number
  31. * @chip: the AIO chip pointer
  32. * @oport_hw: HW port number, one of AUD_HW_XXXX
  33. *
  34. * Find AIO device from device list by HW port number. Volume feature is
  35. * available only in Output and PCM ports, this limitation comes from HW
  36. * specifications.
  37. *
  38. * Return: The pointer of AIO substream if successful, otherwise NULL on error.
  39. */
  40. static struct uniphier_aio_sub *find_volume(struct uniphier_aio_chip *chip,
  41. int oport_hw)
  42. {
  43. int i;
  44. for (i = 0; i < chip->num_aios; i++) {
  45. struct uniphier_aio_sub *sub = &chip->aios[i].sub[0];
  46. if (!sub->swm)
  47. continue;
  48. if (sub->swm->oport.hw == oport_hw)
  49. return sub;
  50. }
  51. return NULL;
  52. }
  53. static bool match_spec(const struct uniphier_aio_spec *spec,
  54. const char *name, int dir)
  55. {
  56. if (dir == SNDRV_PCM_STREAM_PLAYBACK &&
  57. spec->swm.dir != PORT_DIR_OUTPUT) {
  58. return false;
  59. }
  60. if (dir == SNDRV_PCM_STREAM_CAPTURE &&
  61. spec->swm.dir != PORT_DIR_INPUT) {
  62. return false;
  63. }
  64. if (spec->name && strcmp(spec->name, name) == 0)
  65. return true;
  66. if (spec->gname && strcmp(spec->gname, name) == 0)
  67. return true;
  68. return false;
  69. }
  70. /**
  71. * find_spec - find HW specification info by name
  72. * @aio: the AIO device pointer
  73. * @name: name of device
  74. * @direction: the direction of substream, SNDRV_PCM_STREAM_*
  75. *
  76. * Find hardware specification information from list by device name. This
  77. * information is used for telling the difference of SoCs to driver.
  78. *
  79. * Specification list is array of 'struct uniphier_aio_spec' which is defined
  80. * in each drivers (see: aio-i2s.c).
  81. *
  82. * Return: The pointer of hardware specification of AIO if successful,
  83. * otherwise NULL on error.
  84. */
  85. static const struct uniphier_aio_spec *find_spec(struct uniphier_aio *aio,
  86. const char *name,
  87. int direction)
  88. {
  89. const struct uniphier_aio_chip_spec *chip_spec = aio->chip->chip_spec;
  90. int i;
  91. for (i = 0; i < chip_spec->num_specs; i++) {
  92. const struct uniphier_aio_spec *spec = &chip_spec->specs[i];
  93. if (match_spec(spec, name, direction))
  94. return spec;
  95. }
  96. return NULL;
  97. }
  98. /**
  99. * find_divider - find clock divider by frequency
  100. * @aio: the AIO device pointer
  101. * @pll_id: PLL ID, should be AUD_PLL_XX
  102. * @freq: required frequency
  103. *
  104. * Find suitable clock divider by frequency.
  105. *
  106. * Return: The ID of PLL if successful, otherwise negative error value.
  107. */
  108. static int find_divider(struct uniphier_aio *aio, int pll_id, unsigned int freq)
  109. {
  110. struct uniphier_aio_pll *pll;
  111. int mul[] = { 1, 1, 1, 2, };
  112. int div[] = { 2, 3, 1, 3, };
  113. int i;
  114. if (!is_valid_pll(aio->chip, pll_id))
  115. return -EINVAL;
  116. pll = &aio->chip->plls[pll_id];
  117. for (i = 0; i < ARRAY_SIZE(mul); i++)
  118. if (pll->freq * mul[i] / div[i] == freq)
  119. return i;
  120. return -ENOTSUPP;
  121. }
  122. static int uniphier_aio_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  123. unsigned int freq, int dir)
  124. {
  125. struct uniphier_aio *aio = uniphier_priv(dai);
  126. struct device *dev = &aio->chip->pdev->dev;
  127. bool pll_auto = false;
  128. int pll_id, div_id;
  129. switch (clk_id) {
  130. case AUD_CLK_IO:
  131. return -ENOTSUPP;
  132. case AUD_CLK_A1:
  133. pll_id = AUD_PLL_A1;
  134. break;
  135. case AUD_CLK_F1:
  136. pll_id = AUD_PLL_F1;
  137. break;
  138. case AUD_CLK_A2:
  139. pll_id = AUD_PLL_A2;
  140. break;
  141. case AUD_CLK_F2:
  142. pll_id = AUD_PLL_F2;
  143. break;
  144. case AUD_CLK_A:
  145. pll_id = AUD_PLL_A1;
  146. pll_auto = true;
  147. break;
  148. case AUD_CLK_F:
  149. pll_id = AUD_PLL_F1;
  150. pll_auto = true;
  151. break;
  152. case AUD_CLK_APLL:
  153. pll_id = AUD_PLL_APLL;
  154. break;
  155. case AUD_CLK_RX0:
  156. pll_id = AUD_PLL_RX0;
  157. break;
  158. case AUD_CLK_USB0:
  159. pll_id = AUD_PLL_USB0;
  160. break;
  161. case AUD_CLK_HSC0:
  162. pll_id = AUD_PLL_HSC0;
  163. break;
  164. default:
  165. dev_err(dev, "Sysclk(%d) is not supported\n", clk_id);
  166. return -EINVAL;
  167. }
  168. if (pll_auto) {
  169. for (pll_id = 0; pll_id < aio->chip->num_plls; pll_id++) {
  170. div_id = find_divider(aio, pll_id, freq);
  171. if (div_id >= 0) {
  172. aio->plldiv = div_id;
  173. break;
  174. }
  175. }
  176. if (pll_id == aio->chip->num_plls) {
  177. dev_err(dev, "Sysclk frequency is not supported(%d)\n",
  178. freq);
  179. return -EINVAL;
  180. }
  181. }
  182. if (dir == SND_SOC_CLOCK_OUT)
  183. aio->pll_out = pll_id;
  184. else
  185. aio->pll_in = pll_id;
  186. return 0;
  187. }
  188. static int uniphier_aio_set_pll(struct snd_soc_dai *dai, int pll_id,
  189. int source, unsigned int freq_in,
  190. unsigned int freq_out)
  191. {
  192. struct uniphier_aio *aio = uniphier_priv(dai);
  193. int ret;
  194. if (!is_valid_pll(aio->chip, pll_id))
  195. return -EINVAL;
  196. ret = aio_chip_set_pll(aio->chip, pll_id, freq_out);
  197. if (ret < 0)
  198. return ret;
  199. return 0;
  200. }
  201. static int uniphier_aio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  202. {
  203. struct uniphier_aio *aio = uniphier_priv(dai);
  204. struct device *dev = &aio->chip->pdev->dev;
  205. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  206. case SND_SOC_DAIFMT_LEFT_J:
  207. case SND_SOC_DAIFMT_RIGHT_J:
  208. case SND_SOC_DAIFMT_I2S:
  209. aio->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  210. break;
  211. default:
  212. dev_err(dev, "Format is not supported(%d)\n",
  213. fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  214. return -EINVAL;
  215. }
  216. return 0;
  217. }
  218. static int uniphier_aio_startup(struct snd_pcm_substream *substream,
  219. struct snd_soc_dai *dai)
  220. {
  221. struct uniphier_aio *aio = uniphier_priv(dai);
  222. struct uniphier_aio_sub *sub = &aio->sub[substream->stream];
  223. int ret;
  224. sub->substream = substream;
  225. sub->pass_through = 0;
  226. sub->use_mmap = true;
  227. ret = aio_init(sub);
  228. if (ret)
  229. return ret;
  230. return 0;
  231. }
  232. static void uniphier_aio_shutdown(struct snd_pcm_substream *substream,
  233. struct snd_soc_dai *dai)
  234. {
  235. struct uniphier_aio *aio = uniphier_priv(dai);
  236. struct uniphier_aio_sub *sub = &aio->sub[substream->stream];
  237. sub->substream = NULL;
  238. }
  239. static int uniphier_aio_hw_params(struct snd_pcm_substream *substream,
  240. struct snd_pcm_hw_params *params,
  241. struct snd_soc_dai *dai)
  242. {
  243. struct uniphier_aio *aio = uniphier_priv(dai);
  244. struct uniphier_aio_sub *sub = &aio->sub[substream->stream];
  245. struct device *dev = &aio->chip->pdev->dev;
  246. int freq, ret;
  247. switch (params_rate(params)) {
  248. case 48000:
  249. case 32000:
  250. case 24000:
  251. freq = 12288000;
  252. break;
  253. case 44100:
  254. case 22050:
  255. freq = 11289600;
  256. break;
  257. default:
  258. dev_err(dev, "Rate is not supported(%d)\n",
  259. params_rate(params));
  260. return -EINVAL;
  261. }
  262. ret = snd_soc_dai_set_sysclk(dai, AUD_CLK_A,
  263. freq, SND_SOC_CLOCK_OUT);
  264. if (ret)
  265. return ret;
  266. sub->params = *params;
  267. sub->setting = 1;
  268. aio_port_reset(sub);
  269. aio_port_set_volume(sub, sub->vol);
  270. aio_src_reset(sub);
  271. return 0;
  272. }
  273. static int uniphier_aio_hw_free(struct snd_pcm_substream *substream,
  274. struct snd_soc_dai *dai)
  275. {
  276. struct uniphier_aio *aio = uniphier_priv(dai);
  277. struct uniphier_aio_sub *sub = &aio->sub[substream->stream];
  278. sub->setting = 0;
  279. return 0;
  280. }
  281. static int uniphier_aio_prepare(struct snd_pcm_substream *substream,
  282. struct snd_soc_dai *dai)
  283. {
  284. struct uniphier_aio *aio = uniphier_priv(dai);
  285. struct uniphier_aio_sub *sub = &aio->sub[substream->stream];
  286. int ret;
  287. ret = aio_port_set_param(sub, sub->pass_through, &sub->params);
  288. if (ret)
  289. return ret;
  290. ret = aio_src_set_param(sub, &sub->params);
  291. if (ret)
  292. return ret;
  293. aio_port_set_enable(sub, 1);
  294. ret = aio_if_set_param(sub, sub->pass_through);
  295. if (ret)
  296. return ret;
  297. if (sub->swm->type == PORT_TYPE_CONV) {
  298. ret = aio_srcif_set_param(sub);
  299. if (ret)
  300. return ret;
  301. ret = aio_srcch_set_param(sub);
  302. if (ret)
  303. return ret;
  304. aio_srcch_set_enable(sub, 1);
  305. }
  306. return 0;
  307. }
  308. const struct snd_soc_dai_ops uniphier_aio_i2s_ops = {
  309. .set_sysclk = uniphier_aio_set_sysclk,
  310. .set_pll = uniphier_aio_set_pll,
  311. .set_fmt = uniphier_aio_set_fmt,
  312. .startup = uniphier_aio_startup,
  313. .shutdown = uniphier_aio_shutdown,
  314. .hw_params = uniphier_aio_hw_params,
  315. .hw_free = uniphier_aio_hw_free,
  316. .prepare = uniphier_aio_prepare,
  317. };
  318. EXPORT_SYMBOL_GPL(uniphier_aio_i2s_ops);
  319. const struct snd_soc_dai_ops uniphier_aio_spdif_ops = {
  320. .set_sysclk = uniphier_aio_set_sysclk,
  321. .set_pll = uniphier_aio_set_pll,
  322. .startup = uniphier_aio_startup,
  323. .shutdown = uniphier_aio_shutdown,
  324. .hw_params = uniphier_aio_hw_params,
  325. .hw_free = uniphier_aio_hw_free,
  326. .prepare = uniphier_aio_prepare,
  327. };
  328. EXPORT_SYMBOL_GPL(uniphier_aio_spdif_ops);
  329. int uniphier_aio_dai_probe(struct snd_soc_dai *dai)
  330. {
  331. struct uniphier_aio *aio = uniphier_priv(dai);
  332. int i;
  333. for (i = 0; i < ARRAY_SIZE(aio->sub); i++) {
  334. struct uniphier_aio_sub *sub = &aio->sub[i];
  335. const struct uniphier_aio_spec *spec;
  336. spec = find_spec(aio, dai->name, i);
  337. if (!spec)
  338. continue;
  339. sub->swm = &spec->swm;
  340. sub->spec = spec;
  341. sub->vol = AUD_VOL_INIT;
  342. }
  343. aio_iecout_set_enable(aio->chip, true);
  344. aio_chip_init(aio->chip);
  345. aio->chip->active = 1;
  346. return 0;
  347. }
  348. EXPORT_SYMBOL_GPL(uniphier_aio_dai_probe);
  349. int uniphier_aio_dai_remove(struct snd_soc_dai *dai)
  350. {
  351. struct uniphier_aio *aio = uniphier_priv(dai);
  352. aio->chip->active = 0;
  353. return 0;
  354. }
  355. EXPORT_SYMBOL_GPL(uniphier_aio_dai_remove);
  356. int uniphier_aio_dai_suspend(struct snd_soc_dai *dai)
  357. {
  358. struct uniphier_aio *aio = uniphier_priv(dai);
  359. aio->chip->num_wup_aios--;
  360. if (!aio->chip->num_wup_aios) {
  361. reset_control_assert(aio->chip->rst);
  362. clk_disable_unprepare(aio->chip->clk);
  363. }
  364. return 0;
  365. }
  366. EXPORT_SYMBOL_GPL(uniphier_aio_dai_suspend);
  367. int uniphier_aio_dai_resume(struct snd_soc_dai *dai)
  368. {
  369. struct uniphier_aio *aio = uniphier_priv(dai);
  370. int ret, i;
  371. if (!aio->chip->active)
  372. return 0;
  373. if (!aio->chip->num_wup_aios) {
  374. ret = clk_prepare_enable(aio->chip->clk);
  375. if (ret)
  376. return ret;
  377. ret = reset_control_deassert(aio->chip->rst);
  378. if (ret)
  379. goto err_out_clock;
  380. }
  381. aio_iecout_set_enable(aio->chip, true);
  382. aio_chip_init(aio->chip);
  383. for (i = 0; i < ARRAY_SIZE(aio->sub); i++) {
  384. struct uniphier_aio_sub *sub = &aio->sub[i];
  385. if (!sub->spec || !sub->substream)
  386. continue;
  387. ret = aio_init(sub);
  388. if (ret)
  389. goto err_out_reset;
  390. if (!sub->setting)
  391. continue;
  392. aio_port_reset(sub);
  393. aio_src_reset(sub);
  394. }
  395. aio->chip->num_wup_aios++;
  396. return 0;
  397. err_out_reset:
  398. if (!aio->chip->num_wup_aios)
  399. reset_control_assert(aio->chip->rst);
  400. err_out_clock:
  401. if (!aio->chip->num_wup_aios)
  402. clk_disable_unprepare(aio->chip->clk);
  403. return ret;
  404. }
  405. EXPORT_SYMBOL_GPL(uniphier_aio_dai_resume);
  406. static int uniphier_aio_vol_info(struct snd_kcontrol *kcontrol,
  407. struct snd_ctl_elem_info *uinfo)
  408. {
  409. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  410. uinfo->count = 1;
  411. uinfo->value.integer.min = 0;
  412. uinfo->value.integer.max = AUD_VOL_MAX;
  413. return 0;
  414. }
  415. static int uniphier_aio_vol_get(struct snd_kcontrol *kcontrol,
  416. struct snd_ctl_elem_value *ucontrol)
  417. {
  418. struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
  419. struct uniphier_aio_chip *chip = snd_soc_component_get_drvdata(comp);
  420. struct uniphier_aio_sub *sub;
  421. int oport_hw = kcontrol->private_value;
  422. sub = find_volume(chip, oport_hw);
  423. if (!sub)
  424. return 0;
  425. ucontrol->value.integer.value[0] = sub->vol;
  426. return 0;
  427. }
  428. static int uniphier_aio_vol_put(struct snd_kcontrol *kcontrol,
  429. struct snd_ctl_elem_value *ucontrol)
  430. {
  431. struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
  432. struct uniphier_aio_chip *chip = snd_soc_component_get_drvdata(comp);
  433. struct uniphier_aio_sub *sub;
  434. int oport_hw = kcontrol->private_value;
  435. sub = find_volume(chip, oport_hw);
  436. if (!sub)
  437. return 0;
  438. if (sub->vol == ucontrol->value.integer.value[0])
  439. return 0;
  440. sub->vol = ucontrol->value.integer.value[0];
  441. aio_port_set_volume(sub, sub->vol);
  442. return 0;
  443. }
  444. static const struct snd_kcontrol_new uniphier_aio_controls[] = {
  445. {
  446. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  447. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  448. .name = "HPCMOUT1 Volume",
  449. .info = uniphier_aio_vol_info,
  450. .get = uniphier_aio_vol_get,
  451. .put = uniphier_aio_vol_put,
  452. .private_value = AUD_HW_HPCMOUT1,
  453. },
  454. {
  455. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  456. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  457. .name = "PCMOUT1 Volume",
  458. .info = uniphier_aio_vol_info,
  459. .get = uniphier_aio_vol_get,
  460. .put = uniphier_aio_vol_put,
  461. .private_value = AUD_HW_PCMOUT1,
  462. },
  463. {
  464. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  465. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  466. .name = "PCMOUT2 Volume",
  467. .info = uniphier_aio_vol_info,
  468. .get = uniphier_aio_vol_get,
  469. .put = uniphier_aio_vol_put,
  470. .private_value = AUD_HW_PCMOUT2,
  471. },
  472. {
  473. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  474. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  475. .name = "PCMOUT3 Volume",
  476. .info = uniphier_aio_vol_info,
  477. .get = uniphier_aio_vol_get,
  478. .put = uniphier_aio_vol_put,
  479. .private_value = AUD_HW_PCMOUT3,
  480. },
  481. {
  482. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  483. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  484. .name = "HIECOUT1 Volume",
  485. .info = uniphier_aio_vol_info,
  486. .get = uniphier_aio_vol_get,
  487. .put = uniphier_aio_vol_put,
  488. .private_value = AUD_HW_HIECOUT1,
  489. },
  490. {
  491. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  492. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  493. .name = "IECOUT1 Volume",
  494. .info = uniphier_aio_vol_info,
  495. .get = uniphier_aio_vol_get,
  496. .put = uniphier_aio_vol_put,
  497. .private_value = AUD_HW_IECOUT1,
  498. },
  499. };
  500. static const struct snd_soc_component_driver uniphier_aio_component = {
  501. .name = "uniphier-aio",
  502. .controls = uniphier_aio_controls,
  503. .num_controls = ARRAY_SIZE(uniphier_aio_controls),
  504. };
  505. int uniphier_aio_probe(struct platform_device *pdev)
  506. {
  507. struct uniphier_aio_chip *chip;
  508. struct device *dev = &pdev->dev;
  509. int ret, i, j;
  510. chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  511. if (!chip)
  512. return -ENOMEM;
  513. chip->chip_spec = of_device_get_match_data(dev);
  514. if (!chip->chip_spec)
  515. return -EINVAL;
  516. chip->regmap_sg = syscon_regmap_lookup_by_phandle(dev->of_node,
  517. "socionext,syscon");
  518. if (IS_ERR(chip->regmap_sg)) {
  519. if (PTR_ERR(chip->regmap_sg) == -EPROBE_DEFER)
  520. return -EPROBE_DEFER;
  521. chip->regmap_sg = NULL;
  522. }
  523. chip->clk = devm_clk_get(dev, "aio");
  524. if (IS_ERR(chip->clk))
  525. return PTR_ERR(chip->clk);
  526. chip->rst = devm_reset_control_get_shared(dev, "aio");
  527. if (IS_ERR(chip->rst))
  528. return PTR_ERR(chip->rst);
  529. chip->num_aios = chip->chip_spec->num_dais;
  530. chip->num_wup_aios = chip->num_aios;
  531. chip->aios = devm_kcalloc(dev,
  532. chip->num_aios, sizeof(struct uniphier_aio),
  533. GFP_KERNEL);
  534. if (!chip->aios)
  535. return -ENOMEM;
  536. chip->num_plls = chip->chip_spec->num_plls;
  537. chip->plls = devm_kcalloc(dev,
  538. chip->num_plls,
  539. sizeof(struct uniphier_aio_pll),
  540. GFP_KERNEL);
  541. if (!chip->plls)
  542. return -ENOMEM;
  543. memcpy(chip->plls, chip->chip_spec->plls,
  544. sizeof(struct uniphier_aio_pll) * chip->num_plls);
  545. for (i = 0; i < chip->num_aios; i++) {
  546. struct uniphier_aio *aio = &chip->aios[i];
  547. aio->chip = chip;
  548. aio->fmt = SND_SOC_DAIFMT_I2S;
  549. for (j = 0; j < ARRAY_SIZE(aio->sub); j++) {
  550. struct uniphier_aio_sub *sub = &aio->sub[j];
  551. sub->aio = aio;
  552. spin_lock_init(&sub->lock);
  553. }
  554. }
  555. chip->pdev = pdev;
  556. platform_set_drvdata(pdev, chip);
  557. ret = clk_prepare_enable(chip->clk);
  558. if (ret)
  559. return ret;
  560. ret = reset_control_deassert(chip->rst);
  561. if (ret)
  562. goto err_out_clock;
  563. ret = devm_snd_soc_register_component(dev, &uniphier_aio_component,
  564. chip->chip_spec->dais,
  565. chip->chip_spec->num_dais);
  566. if (ret) {
  567. dev_err(dev, "Register component failed.\n");
  568. goto err_out_reset;
  569. }
  570. ret = uniphier_aiodma_soc_register_platform(pdev);
  571. if (ret) {
  572. dev_err(dev, "Register platform failed.\n");
  573. goto err_out_reset;
  574. }
  575. return 0;
  576. err_out_reset:
  577. reset_control_assert(chip->rst);
  578. err_out_clock:
  579. clk_disable_unprepare(chip->clk);
  580. return ret;
  581. }
  582. EXPORT_SYMBOL_GPL(uniphier_aio_probe);
  583. int uniphier_aio_remove(struct platform_device *pdev)
  584. {
  585. struct uniphier_aio_chip *chip = platform_get_drvdata(pdev);
  586. reset_control_assert(chip->rst);
  587. clk_disable_unprepare(chip->clk);
  588. return 0;
  589. }
  590. EXPORT_SYMBOL_GPL(uniphier_aio_remove);
  591. MODULE_AUTHOR("Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>");
  592. MODULE_DESCRIPTION("UniPhier AIO CPU DAI driver.");
  593. MODULE_LICENSE("GPL v2");