tegra186_bpmp.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <dm/lists.h>
  8. #include <dm/root.h>
  9. #include <mailbox.h>
  10. #include <misc.h>
  11. #include <asm/arch-tegra/bpmp_abi.h>
  12. #include <asm/arch-tegra/ivc.h>
  13. #define BPMP_IVC_FRAME_COUNT 1
  14. #define BPMP_IVC_FRAME_SIZE 128
  15. #define BPMP_FLAG_DO_ACK BIT(0)
  16. #define BPMP_FLAG_RING_DOORBELL BIT(1)
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct tegra186_bpmp {
  19. struct mbox_chan mbox;
  20. struct tegra_ivc ivc;
  21. };
  22. static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg,
  23. int tx_size, void *rx_msg, int rx_size)
  24. {
  25. struct tegra186_bpmp *priv = dev_get_priv(dev);
  26. int ret, err;
  27. void *ivc_frame;
  28. struct mrq_request *req;
  29. struct mrq_response *resp;
  30. ulong start_time;
  31. debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n",
  32. __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv);
  33. if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE))
  34. return -EINVAL;
  35. ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame);
  36. if (ret) {
  37. pr_err("tegra_ivc_write_get_next_frame() failed: %d\n", ret);
  38. return ret;
  39. }
  40. req = ivc_frame;
  41. req->mrq = mrq;
  42. req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL;
  43. memcpy(req + 1, tx_msg, tx_size);
  44. ret = tegra_ivc_write_advance(&priv->ivc);
  45. if (ret) {
  46. pr_err("tegra_ivc_write_advance() failed: %d\n", ret);
  47. return ret;
  48. }
  49. start_time = timer_get_us();
  50. for (;;) {
  51. ret = tegra_ivc_channel_notified(&priv->ivc);
  52. if (ret) {
  53. pr_err("tegra_ivc_channel_notified() failed: %d\n", ret);
  54. return ret;
  55. }
  56. ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame);
  57. if (!ret)
  58. break;
  59. /* Timeout 20ms; roughly 10x current max observed duration */
  60. if ((timer_get_us() - start_time) > 20 * 1000) {
  61. pr_err("tegra_ivc_read_get_next_frame() timed out (%d)\n",
  62. ret);
  63. return -ETIMEDOUT;
  64. }
  65. }
  66. resp = ivc_frame;
  67. err = resp->err;
  68. if (!err && rx_msg && rx_size)
  69. memcpy(rx_msg, resp + 1, rx_size);
  70. ret = tegra_ivc_read_advance(&priv->ivc);
  71. if (ret) {
  72. pr_err("tegra_ivc_write_advance() failed: %d\n", ret);
  73. return ret;
  74. }
  75. if (err) {
  76. pr_err("BPMP responded with error %d\n", err);
  77. /* err isn't a U-Boot error code, so don't that */
  78. return -EIO;
  79. }
  80. return rx_size;
  81. }
  82. /**
  83. * The BPMP exposes multiple different services. We create a sub-device for
  84. * each separate type of service, since each device must be of the appropriate
  85. * UCLASS.
  86. */
  87. static int tegra186_bpmp_bind(struct udevice *dev)
  88. {
  89. int ret;
  90. struct udevice *child;
  91. debug("%s(dev=%p)\n", __func__, dev);
  92. ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
  93. dev_ofnode(dev), &child);
  94. if (ret)
  95. return ret;
  96. ret = device_bind_driver_to_node(dev, "tegra186_reset",
  97. "tegra186_reset", dev_ofnode(dev),
  98. &child);
  99. if (ret)
  100. return ret;
  101. ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
  102. "tegra186_power_domain",
  103. dev_ofnode(dev), &child);
  104. if (ret)
  105. return ret;
  106. ret = dm_scan_fdt_dev(dev);
  107. if (ret)
  108. return ret;
  109. return 0;
  110. }
  111. static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index)
  112. {
  113. int ret;
  114. struct fdtdec_phandle_args args;
  115. fdt_addr_t reg;
  116. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
  117. "shmem", NULL, 0, index, &args);
  118. if (ret < 0) {
  119. pr_err("fdtdec_parse_phandle_with_args() failed: %d\n", ret);
  120. return ret;
  121. }
  122. reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node,
  123. "reg", 0, NULL, true);
  124. if (reg == FDT_ADDR_T_NONE) {
  125. pr_err("fdtdec_get_addr_size_auto_noparent() failed\n");
  126. return -ENODEV;
  127. }
  128. return reg;
  129. }
  130. static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc)
  131. {
  132. struct tegra186_bpmp *priv =
  133. container_of(ivc, struct tegra186_bpmp, ivc);
  134. int ret;
  135. ret = mbox_send(&priv->mbox, NULL);
  136. if (ret)
  137. pr_err("mbox_send() failed: %d\n", ret);
  138. }
  139. static int tegra186_bpmp_probe(struct udevice *dev)
  140. {
  141. struct tegra186_bpmp *priv = dev_get_priv(dev);
  142. int ret;
  143. ulong tx_base, rx_base, start_time;
  144. debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
  145. ret = mbox_get_by_index(dev, 0, &priv->mbox);
  146. if (ret) {
  147. pr_err("mbox_get_by_index() failed: %d\n", ret);
  148. return ret;
  149. }
  150. tx_base = tegra186_bpmp_get_shmem(dev, 0);
  151. if (IS_ERR_VALUE(tx_base)) {
  152. pr_err("tegra186_bpmp_get_shmem failed for tx_base\n");
  153. return tx_base;
  154. }
  155. rx_base = tegra186_bpmp_get_shmem(dev, 1);
  156. if (IS_ERR_VALUE(rx_base)) {
  157. pr_err("tegra186_bpmp_get_shmem failed for rx_base\n");
  158. return rx_base;
  159. }
  160. debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base);
  161. ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT,
  162. BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify);
  163. if (ret) {
  164. pr_err("tegra_ivc_init() failed: %d\n", ret);
  165. return ret;
  166. }
  167. tegra_ivc_channel_reset(&priv->ivc);
  168. start_time = timer_get_us();
  169. for (;;) {
  170. ret = tegra_ivc_channel_notified(&priv->ivc);
  171. if (!ret)
  172. break;
  173. /* Timeout 100ms */
  174. if ((timer_get_us() - start_time) > 100 * 1000) {
  175. pr_err("Initial IVC reset timed out (%d)\n", ret);
  176. ret = -ETIMEDOUT;
  177. goto err_free_mbox;
  178. }
  179. }
  180. return 0;
  181. err_free_mbox:
  182. mbox_free(&priv->mbox);
  183. return ret;
  184. }
  185. static int tegra186_bpmp_remove(struct udevice *dev)
  186. {
  187. struct tegra186_bpmp *priv = dev_get_priv(dev);
  188. debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
  189. mbox_free(&priv->mbox);
  190. return 0;
  191. }
  192. static struct misc_ops tegra186_bpmp_ops = {
  193. .call = tegra186_bpmp_call,
  194. };
  195. static const struct udevice_id tegra186_bpmp_ids[] = {
  196. { .compatible = "nvidia,tegra186-bpmp" },
  197. { }
  198. };
  199. U_BOOT_DRIVER(tegra186_bpmp) = {
  200. .name = "tegra186_bpmp",
  201. .id = UCLASS_MISC,
  202. .of_match = tegra186_bpmp_ids,
  203. .bind = tegra186_bpmp_bind,
  204. .probe = tegra186_bpmp_probe,
  205. .remove = tegra186_bpmp_remove,
  206. .ops = &tegra186_bpmp_ops,
  207. .priv_auto_alloc_size = sizeof(struct tegra186_bpmp),
  208. };