intel-pt.c 64 KB

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  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <inttypes.h>
  16. #include <stdio.h>
  17. #include <stdbool.h>
  18. #include <errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include "../perf.h"
  22. #include "session.h"
  23. #include "machine.h"
  24. #include "memswap.h"
  25. #include "sort.h"
  26. #include "tool.h"
  27. #include "event.h"
  28. #include "evlist.h"
  29. #include "evsel.h"
  30. #include "map.h"
  31. #include "color.h"
  32. #include "util.h"
  33. #include "thread.h"
  34. #include "thread-stack.h"
  35. #include "symbol.h"
  36. #include "callchain.h"
  37. #include "dso.h"
  38. #include "debug.h"
  39. #include "auxtrace.h"
  40. #include "tsc.h"
  41. #include "intel-pt.h"
  42. #include "config.h"
  43. #include "intel-pt-decoder/intel-pt-log.h"
  44. #include "intel-pt-decoder/intel-pt-decoder.h"
  45. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  46. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  47. #define MAX_TIMESTAMP (~0ULL)
  48. struct intel_pt {
  49. struct auxtrace auxtrace;
  50. struct auxtrace_queues queues;
  51. struct auxtrace_heap heap;
  52. u32 auxtrace_type;
  53. struct perf_session *session;
  54. struct machine *machine;
  55. struct perf_evsel *switch_evsel;
  56. struct thread *unknown_thread;
  57. bool timeless_decoding;
  58. bool sampling_mode;
  59. bool snapshot_mode;
  60. bool per_cpu_mmaps;
  61. bool have_tsc;
  62. bool data_queued;
  63. bool est_tsc;
  64. bool sync_switch;
  65. bool mispred_all;
  66. int have_sched_switch;
  67. u32 pmu_type;
  68. u64 kernel_start;
  69. u64 switch_ip;
  70. u64 ptss_ip;
  71. struct perf_tsc_conversion tc;
  72. bool cap_user_time_zero;
  73. struct itrace_synth_opts synth_opts;
  74. bool sample_instructions;
  75. u64 instructions_sample_type;
  76. u64 instructions_id;
  77. bool sample_branches;
  78. u32 branches_filter;
  79. u64 branches_sample_type;
  80. u64 branches_id;
  81. bool sample_transactions;
  82. u64 transactions_sample_type;
  83. u64 transactions_id;
  84. bool sample_ptwrites;
  85. u64 ptwrites_sample_type;
  86. u64 ptwrites_id;
  87. bool sample_pwr_events;
  88. u64 pwr_events_sample_type;
  89. u64 mwait_id;
  90. u64 pwre_id;
  91. u64 exstop_id;
  92. u64 pwrx_id;
  93. u64 cbr_id;
  94. u64 tsc_bit;
  95. u64 mtc_bit;
  96. u64 mtc_freq_bits;
  97. u32 tsc_ctc_ratio_n;
  98. u32 tsc_ctc_ratio_d;
  99. u64 cyc_bit;
  100. u64 noretcomp_bit;
  101. unsigned max_non_turbo_ratio;
  102. unsigned cbr2khz;
  103. unsigned long num_events;
  104. char *filter;
  105. struct addr_filters filts;
  106. };
  107. enum switch_state {
  108. INTEL_PT_SS_NOT_TRACING,
  109. INTEL_PT_SS_UNKNOWN,
  110. INTEL_PT_SS_TRACING,
  111. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  112. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  113. };
  114. struct intel_pt_queue {
  115. struct intel_pt *pt;
  116. unsigned int queue_nr;
  117. struct auxtrace_buffer *buffer;
  118. struct auxtrace_buffer *old_buffer;
  119. void *decoder;
  120. const struct intel_pt_state *state;
  121. struct ip_callchain *chain;
  122. struct branch_stack *last_branch;
  123. struct branch_stack *last_branch_rb;
  124. size_t last_branch_pos;
  125. union perf_event *event_buf;
  126. bool on_heap;
  127. bool stop;
  128. bool step_through_buffers;
  129. bool use_buffer_pid_tid;
  130. bool sync_switch;
  131. pid_t pid, tid;
  132. int cpu;
  133. int switch_state;
  134. pid_t next_tid;
  135. struct thread *thread;
  136. bool exclude_kernel;
  137. bool have_sample;
  138. u64 time;
  139. u64 timestamp;
  140. u32 flags;
  141. u16 insn_len;
  142. u64 last_insn_cnt;
  143. char insn[INTEL_PT_INSN_BUF_SZ];
  144. };
  145. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  146. unsigned char *buf, size_t len)
  147. {
  148. struct intel_pt_pkt packet;
  149. size_t pos = 0;
  150. int ret, pkt_len, i;
  151. char desc[INTEL_PT_PKT_DESC_MAX];
  152. const char *color = PERF_COLOR_BLUE;
  153. color_fprintf(stdout, color,
  154. ". ... Intel Processor Trace data: size %zu bytes\n",
  155. len);
  156. while (len) {
  157. ret = intel_pt_get_packet(buf, len, &packet);
  158. if (ret > 0)
  159. pkt_len = ret;
  160. else
  161. pkt_len = 1;
  162. printf(".");
  163. color_fprintf(stdout, color, " %08x: ", pos);
  164. for (i = 0; i < pkt_len; i++)
  165. color_fprintf(stdout, color, " %02x", buf[i]);
  166. for (; i < 16; i++)
  167. color_fprintf(stdout, color, " ");
  168. if (ret > 0) {
  169. ret = intel_pt_pkt_desc(&packet, desc,
  170. INTEL_PT_PKT_DESC_MAX);
  171. if (ret > 0)
  172. color_fprintf(stdout, color, " %s\n", desc);
  173. } else {
  174. color_fprintf(stdout, color, " Bad packet!\n");
  175. }
  176. pos += pkt_len;
  177. buf += pkt_len;
  178. len -= pkt_len;
  179. }
  180. }
  181. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  182. size_t len)
  183. {
  184. printf(".\n");
  185. intel_pt_dump(pt, buf, len);
  186. }
  187. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  188. struct auxtrace_buffer *b)
  189. {
  190. bool consecutive = false;
  191. void *start;
  192. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  193. pt->have_tsc, &consecutive);
  194. if (!start)
  195. return -EINVAL;
  196. b->use_size = b->data + b->size - start;
  197. b->use_data = start;
  198. if (b->use_size && consecutive)
  199. b->consecutive = true;
  200. return 0;
  201. }
  202. /* This function assumes data is processed sequentially only */
  203. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  204. {
  205. struct intel_pt_queue *ptq = data;
  206. struct auxtrace_buffer *buffer = ptq->buffer;
  207. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  208. struct auxtrace_queue *queue;
  209. bool might_overlap;
  210. if (ptq->stop) {
  211. b->len = 0;
  212. return 0;
  213. }
  214. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  215. buffer = auxtrace_buffer__next(queue, buffer);
  216. if (!buffer) {
  217. if (old_buffer)
  218. auxtrace_buffer__drop_data(old_buffer);
  219. b->len = 0;
  220. return 0;
  221. }
  222. ptq->buffer = buffer;
  223. if (!buffer->data) {
  224. int fd = perf_data__fd(ptq->pt->session->data);
  225. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  226. if (!buffer->data)
  227. return -ENOMEM;
  228. }
  229. might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
  230. if (might_overlap && !buffer->consecutive && old_buffer &&
  231. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  232. return -ENOMEM;
  233. if (buffer->use_data) {
  234. b->len = buffer->use_size;
  235. b->buf = buffer->use_data;
  236. } else {
  237. b->len = buffer->size;
  238. b->buf = buffer->data;
  239. }
  240. b->ref_timestamp = buffer->reference;
  241. if (!old_buffer || (might_overlap && !buffer->consecutive)) {
  242. b->consecutive = false;
  243. b->trace_nr = buffer->buffer_nr + 1;
  244. } else {
  245. b->consecutive = true;
  246. }
  247. if (ptq->step_through_buffers)
  248. ptq->stop = true;
  249. if (b->len) {
  250. if (old_buffer)
  251. auxtrace_buffer__drop_data(old_buffer);
  252. ptq->old_buffer = buffer;
  253. } else {
  254. auxtrace_buffer__drop_data(buffer);
  255. return intel_pt_get_trace(b, data);
  256. }
  257. return 0;
  258. }
  259. struct intel_pt_cache_entry {
  260. struct auxtrace_cache_entry entry;
  261. u64 insn_cnt;
  262. u64 byte_cnt;
  263. enum intel_pt_insn_op op;
  264. enum intel_pt_insn_branch branch;
  265. int length;
  266. int32_t rel;
  267. char insn[INTEL_PT_INSN_BUF_SZ];
  268. };
  269. static int intel_pt_config_div(const char *var, const char *value, void *data)
  270. {
  271. int *d = data;
  272. long val;
  273. if (!strcmp(var, "intel-pt.cache-divisor")) {
  274. val = strtol(value, NULL, 0);
  275. if (val > 0 && val <= INT_MAX)
  276. *d = val;
  277. }
  278. return 0;
  279. }
  280. static int intel_pt_cache_divisor(void)
  281. {
  282. static int d;
  283. if (d)
  284. return d;
  285. perf_config(intel_pt_config_div, &d);
  286. if (!d)
  287. d = 64;
  288. return d;
  289. }
  290. static unsigned int intel_pt_cache_size(struct dso *dso,
  291. struct machine *machine)
  292. {
  293. off_t size;
  294. size = dso__data_size(dso, machine);
  295. size /= intel_pt_cache_divisor();
  296. if (size < 1000)
  297. return 10;
  298. if (size > (1 << 21))
  299. return 21;
  300. return 32 - __builtin_clz(size);
  301. }
  302. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  303. struct machine *machine)
  304. {
  305. struct auxtrace_cache *c;
  306. unsigned int bits;
  307. if (dso->auxtrace_cache)
  308. return dso->auxtrace_cache;
  309. bits = intel_pt_cache_size(dso, machine);
  310. /* Ignoring cache creation failure */
  311. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  312. dso->auxtrace_cache = c;
  313. return c;
  314. }
  315. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  316. u64 offset, u64 insn_cnt, u64 byte_cnt,
  317. struct intel_pt_insn *intel_pt_insn)
  318. {
  319. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  320. struct intel_pt_cache_entry *e;
  321. int err;
  322. if (!c)
  323. return -ENOMEM;
  324. e = auxtrace_cache__alloc_entry(c);
  325. if (!e)
  326. return -ENOMEM;
  327. e->insn_cnt = insn_cnt;
  328. e->byte_cnt = byte_cnt;
  329. e->op = intel_pt_insn->op;
  330. e->branch = intel_pt_insn->branch;
  331. e->length = intel_pt_insn->length;
  332. e->rel = intel_pt_insn->rel;
  333. memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
  334. err = auxtrace_cache__add(c, offset, &e->entry);
  335. if (err)
  336. auxtrace_cache__free_entry(c, e);
  337. return err;
  338. }
  339. static struct intel_pt_cache_entry *
  340. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  341. {
  342. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  343. if (!c)
  344. return NULL;
  345. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  346. }
  347. static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip)
  348. {
  349. return ip >= pt->kernel_start ?
  350. PERF_RECORD_MISC_KERNEL :
  351. PERF_RECORD_MISC_USER;
  352. }
  353. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  354. uint64_t *insn_cnt_ptr, uint64_t *ip,
  355. uint64_t to_ip, uint64_t max_insn_cnt,
  356. void *data)
  357. {
  358. struct intel_pt_queue *ptq = data;
  359. struct machine *machine = ptq->pt->machine;
  360. struct thread *thread;
  361. struct addr_location al;
  362. unsigned char buf[INTEL_PT_INSN_BUF_SZ];
  363. ssize_t len;
  364. int x86_64;
  365. u8 cpumode;
  366. u64 offset, start_offset, start_ip;
  367. u64 insn_cnt = 0;
  368. bool one_map = true;
  369. intel_pt_insn->length = 0;
  370. if (to_ip && *ip == to_ip)
  371. goto out_no_cache;
  372. cpumode = intel_pt_cpumode(ptq->pt, *ip);
  373. thread = ptq->thread;
  374. if (!thread) {
  375. if (cpumode != PERF_RECORD_MISC_KERNEL)
  376. return -EINVAL;
  377. thread = ptq->pt->unknown_thread;
  378. }
  379. while (1) {
  380. if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
  381. return -EINVAL;
  382. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  383. dso__data_status_seen(al.map->dso,
  384. DSO_DATA_STATUS_SEEN_ITRACE))
  385. return -ENOENT;
  386. offset = al.map->map_ip(al.map, *ip);
  387. if (!to_ip && one_map) {
  388. struct intel_pt_cache_entry *e;
  389. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  390. if (e &&
  391. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  392. *insn_cnt_ptr = e->insn_cnt;
  393. *ip += e->byte_cnt;
  394. intel_pt_insn->op = e->op;
  395. intel_pt_insn->branch = e->branch;
  396. intel_pt_insn->length = e->length;
  397. intel_pt_insn->rel = e->rel;
  398. memcpy(intel_pt_insn->buf, e->insn,
  399. INTEL_PT_INSN_BUF_SZ);
  400. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  401. return 0;
  402. }
  403. }
  404. start_offset = offset;
  405. start_ip = *ip;
  406. /* Load maps to ensure dso->is_64_bit has been updated */
  407. map__load(al.map);
  408. x86_64 = al.map->dso->is_64_bit;
  409. while (1) {
  410. len = dso__data_read_offset(al.map->dso, machine,
  411. offset, buf,
  412. INTEL_PT_INSN_BUF_SZ);
  413. if (len <= 0)
  414. return -EINVAL;
  415. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  416. return -EINVAL;
  417. intel_pt_log_insn(intel_pt_insn, *ip);
  418. insn_cnt += 1;
  419. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  420. goto out;
  421. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  422. goto out_no_cache;
  423. *ip += intel_pt_insn->length;
  424. if (to_ip && *ip == to_ip)
  425. goto out_no_cache;
  426. if (*ip >= al.map->end)
  427. break;
  428. offset += intel_pt_insn->length;
  429. }
  430. one_map = false;
  431. }
  432. out:
  433. *insn_cnt_ptr = insn_cnt;
  434. if (!one_map)
  435. goto out_no_cache;
  436. /*
  437. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  438. * entries.
  439. */
  440. if (to_ip) {
  441. struct intel_pt_cache_entry *e;
  442. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  443. if (e)
  444. return 0;
  445. }
  446. /* Ignore cache errors */
  447. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  448. *ip - start_ip, intel_pt_insn);
  449. return 0;
  450. out_no_cache:
  451. *insn_cnt_ptr = insn_cnt;
  452. return 0;
  453. }
  454. static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
  455. uint64_t offset, const char *filename)
  456. {
  457. struct addr_filter *filt;
  458. bool have_filter = false;
  459. bool hit_tracestop = false;
  460. bool hit_filter = false;
  461. list_for_each_entry(filt, &pt->filts.head, list) {
  462. if (filt->start)
  463. have_filter = true;
  464. if ((filename && !filt->filename) ||
  465. (!filename && filt->filename) ||
  466. (filename && strcmp(filename, filt->filename)))
  467. continue;
  468. if (!(offset >= filt->addr && offset < filt->addr + filt->size))
  469. continue;
  470. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
  471. ip, offset, filename ? filename : "[kernel]",
  472. filt->start ? "filter" : "stop",
  473. filt->addr, filt->size);
  474. if (filt->start)
  475. hit_filter = true;
  476. else
  477. hit_tracestop = true;
  478. }
  479. if (!hit_tracestop && !hit_filter)
  480. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
  481. ip, offset, filename ? filename : "[kernel]");
  482. return hit_tracestop || (have_filter && !hit_filter);
  483. }
  484. static int __intel_pt_pgd_ip(uint64_t ip, void *data)
  485. {
  486. struct intel_pt_queue *ptq = data;
  487. struct thread *thread;
  488. struct addr_location al;
  489. u8 cpumode;
  490. u64 offset;
  491. if (ip >= ptq->pt->kernel_start)
  492. return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
  493. cpumode = PERF_RECORD_MISC_USER;
  494. thread = ptq->thread;
  495. if (!thread)
  496. return -EINVAL;
  497. if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
  498. return -EINVAL;
  499. offset = al.map->map_ip(al.map, ip);
  500. return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
  501. al.map->dso->long_name);
  502. }
  503. static bool intel_pt_pgd_ip(uint64_t ip, void *data)
  504. {
  505. return __intel_pt_pgd_ip(ip, data) > 0;
  506. }
  507. static bool intel_pt_get_config(struct intel_pt *pt,
  508. struct perf_event_attr *attr, u64 *config)
  509. {
  510. if (attr->type == pt->pmu_type) {
  511. if (config)
  512. *config = attr->config;
  513. return true;
  514. }
  515. return false;
  516. }
  517. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  518. {
  519. struct perf_evsel *evsel;
  520. evlist__for_each_entry(pt->session->evlist, evsel) {
  521. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  522. !evsel->attr.exclude_kernel)
  523. return false;
  524. }
  525. return true;
  526. }
  527. static bool intel_pt_return_compression(struct intel_pt *pt)
  528. {
  529. struct perf_evsel *evsel;
  530. u64 config;
  531. if (!pt->noretcomp_bit)
  532. return true;
  533. evlist__for_each_entry(pt->session->evlist, evsel) {
  534. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  535. (config & pt->noretcomp_bit))
  536. return false;
  537. }
  538. return true;
  539. }
  540. static bool intel_pt_branch_enable(struct intel_pt *pt)
  541. {
  542. struct perf_evsel *evsel;
  543. u64 config;
  544. evlist__for_each_entry(pt->session->evlist, evsel) {
  545. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  546. (config & 1) && !(config & 0x2000))
  547. return false;
  548. }
  549. return true;
  550. }
  551. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  552. {
  553. struct perf_evsel *evsel;
  554. unsigned int shift;
  555. u64 config;
  556. if (!pt->mtc_freq_bits)
  557. return 0;
  558. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  559. config >>= 1;
  560. evlist__for_each_entry(pt->session->evlist, evsel) {
  561. if (intel_pt_get_config(pt, &evsel->attr, &config))
  562. return (config & pt->mtc_freq_bits) >> shift;
  563. }
  564. return 0;
  565. }
  566. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  567. {
  568. struct perf_evsel *evsel;
  569. bool timeless_decoding = true;
  570. u64 config;
  571. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  572. return true;
  573. evlist__for_each_entry(pt->session->evlist, evsel) {
  574. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  575. return true;
  576. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  577. if (config & pt->tsc_bit)
  578. timeless_decoding = false;
  579. else
  580. return true;
  581. }
  582. }
  583. return timeless_decoding;
  584. }
  585. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  586. {
  587. struct perf_evsel *evsel;
  588. evlist__for_each_entry(pt->session->evlist, evsel) {
  589. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  590. !evsel->attr.exclude_kernel)
  591. return true;
  592. }
  593. return false;
  594. }
  595. static bool intel_pt_have_tsc(struct intel_pt *pt)
  596. {
  597. struct perf_evsel *evsel;
  598. bool have_tsc = false;
  599. u64 config;
  600. if (!pt->tsc_bit)
  601. return false;
  602. evlist__for_each_entry(pt->session->evlist, evsel) {
  603. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  604. if (config & pt->tsc_bit)
  605. have_tsc = true;
  606. else
  607. return false;
  608. }
  609. }
  610. return have_tsc;
  611. }
  612. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  613. {
  614. u64 quot, rem;
  615. quot = ns / pt->tc.time_mult;
  616. rem = ns % pt->tc.time_mult;
  617. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  618. pt->tc.time_mult;
  619. }
  620. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  621. unsigned int queue_nr)
  622. {
  623. struct intel_pt_params params = { .get_trace = 0, };
  624. struct perf_env *env = pt->machine->env;
  625. struct intel_pt_queue *ptq;
  626. ptq = zalloc(sizeof(struct intel_pt_queue));
  627. if (!ptq)
  628. return NULL;
  629. if (pt->synth_opts.callchain) {
  630. size_t sz = sizeof(struct ip_callchain);
  631. /* Add 1 to callchain_sz for callchain context */
  632. sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
  633. ptq->chain = zalloc(sz);
  634. if (!ptq->chain)
  635. goto out_free;
  636. }
  637. if (pt->synth_opts.last_branch) {
  638. size_t sz = sizeof(struct branch_stack);
  639. sz += pt->synth_opts.last_branch_sz *
  640. sizeof(struct branch_entry);
  641. ptq->last_branch = zalloc(sz);
  642. if (!ptq->last_branch)
  643. goto out_free;
  644. ptq->last_branch_rb = zalloc(sz);
  645. if (!ptq->last_branch_rb)
  646. goto out_free;
  647. }
  648. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  649. if (!ptq->event_buf)
  650. goto out_free;
  651. ptq->pt = pt;
  652. ptq->queue_nr = queue_nr;
  653. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  654. ptq->pid = -1;
  655. ptq->tid = -1;
  656. ptq->cpu = -1;
  657. ptq->next_tid = -1;
  658. params.get_trace = intel_pt_get_trace;
  659. params.walk_insn = intel_pt_walk_next_insn;
  660. params.data = ptq;
  661. params.return_compression = intel_pt_return_compression(pt);
  662. params.branch_enable = intel_pt_branch_enable(pt);
  663. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  664. params.mtc_period = intel_pt_mtc_period(pt);
  665. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  666. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  667. if (pt->filts.cnt > 0)
  668. params.pgd_ip = intel_pt_pgd_ip;
  669. if (pt->synth_opts.instructions) {
  670. if (pt->synth_opts.period) {
  671. switch (pt->synth_opts.period_type) {
  672. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  673. params.period_type =
  674. INTEL_PT_PERIOD_INSTRUCTIONS;
  675. params.period = pt->synth_opts.period;
  676. break;
  677. case PERF_ITRACE_PERIOD_TICKS:
  678. params.period_type = INTEL_PT_PERIOD_TICKS;
  679. params.period = pt->synth_opts.period;
  680. break;
  681. case PERF_ITRACE_PERIOD_NANOSECS:
  682. params.period_type = INTEL_PT_PERIOD_TICKS;
  683. params.period = intel_pt_ns_to_ticks(pt,
  684. pt->synth_opts.period);
  685. break;
  686. default:
  687. break;
  688. }
  689. }
  690. if (!params.period) {
  691. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  692. params.period = 1;
  693. }
  694. }
  695. if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
  696. params.flags |= INTEL_PT_FUP_WITH_NLIP;
  697. ptq->decoder = intel_pt_decoder_new(&params);
  698. if (!ptq->decoder)
  699. goto out_free;
  700. return ptq;
  701. out_free:
  702. zfree(&ptq->event_buf);
  703. zfree(&ptq->last_branch);
  704. zfree(&ptq->last_branch_rb);
  705. zfree(&ptq->chain);
  706. free(ptq);
  707. return NULL;
  708. }
  709. static void intel_pt_free_queue(void *priv)
  710. {
  711. struct intel_pt_queue *ptq = priv;
  712. if (!ptq)
  713. return;
  714. thread__zput(ptq->thread);
  715. intel_pt_decoder_free(ptq->decoder);
  716. zfree(&ptq->event_buf);
  717. zfree(&ptq->last_branch);
  718. zfree(&ptq->last_branch_rb);
  719. zfree(&ptq->chain);
  720. free(ptq);
  721. }
  722. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  723. struct auxtrace_queue *queue)
  724. {
  725. struct intel_pt_queue *ptq = queue->priv;
  726. if (queue->tid == -1 || pt->have_sched_switch) {
  727. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  728. if (ptq->tid == -1)
  729. ptq->pid = -1;
  730. thread__zput(ptq->thread);
  731. }
  732. if (!ptq->thread && ptq->tid != -1)
  733. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  734. if (ptq->thread) {
  735. ptq->pid = ptq->thread->pid_;
  736. if (queue->cpu == -1)
  737. ptq->cpu = ptq->thread->cpu;
  738. }
  739. }
  740. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  741. {
  742. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  743. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  744. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  745. if (ptq->state->to_ip)
  746. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  747. PERF_IP_FLAG_ASYNC |
  748. PERF_IP_FLAG_INTERRUPT;
  749. else
  750. ptq->flags = PERF_IP_FLAG_BRANCH |
  751. PERF_IP_FLAG_TRACE_END;
  752. ptq->insn_len = 0;
  753. } else {
  754. if (ptq->state->from_ip)
  755. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  756. else
  757. ptq->flags = PERF_IP_FLAG_BRANCH |
  758. PERF_IP_FLAG_TRACE_BEGIN;
  759. if (ptq->state->flags & INTEL_PT_IN_TX)
  760. ptq->flags |= PERF_IP_FLAG_IN_TX;
  761. ptq->insn_len = ptq->state->insn_len;
  762. memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
  763. }
  764. }
  765. static int intel_pt_setup_queue(struct intel_pt *pt,
  766. struct auxtrace_queue *queue,
  767. unsigned int queue_nr)
  768. {
  769. struct intel_pt_queue *ptq = queue->priv;
  770. if (list_empty(&queue->head))
  771. return 0;
  772. if (!ptq) {
  773. ptq = intel_pt_alloc_queue(pt, queue_nr);
  774. if (!ptq)
  775. return -ENOMEM;
  776. queue->priv = ptq;
  777. if (queue->cpu != -1)
  778. ptq->cpu = queue->cpu;
  779. ptq->tid = queue->tid;
  780. if (pt->sampling_mode && !pt->snapshot_mode &&
  781. pt->timeless_decoding)
  782. ptq->step_through_buffers = true;
  783. ptq->sync_switch = pt->sync_switch;
  784. }
  785. if (!ptq->on_heap &&
  786. (!ptq->sync_switch ||
  787. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  788. const struct intel_pt_state *state;
  789. int ret;
  790. if (pt->timeless_decoding)
  791. return 0;
  792. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  793. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  794. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  795. while (1) {
  796. state = intel_pt_decode(ptq->decoder);
  797. if (state->err) {
  798. if (state->err == INTEL_PT_ERR_NODATA) {
  799. intel_pt_log("queue %u has no timestamp\n",
  800. queue_nr);
  801. return 0;
  802. }
  803. continue;
  804. }
  805. if (state->timestamp)
  806. break;
  807. }
  808. ptq->timestamp = state->timestamp;
  809. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  810. queue_nr, ptq->timestamp);
  811. ptq->state = state;
  812. ptq->have_sample = true;
  813. intel_pt_sample_flags(ptq);
  814. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  815. if (ret)
  816. return ret;
  817. ptq->on_heap = true;
  818. }
  819. return 0;
  820. }
  821. static int intel_pt_setup_queues(struct intel_pt *pt)
  822. {
  823. unsigned int i;
  824. int ret;
  825. for (i = 0; i < pt->queues.nr_queues; i++) {
  826. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  827. if (ret)
  828. return ret;
  829. }
  830. return 0;
  831. }
  832. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  833. {
  834. struct branch_stack *bs_src = ptq->last_branch_rb;
  835. struct branch_stack *bs_dst = ptq->last_branch;
  836. size_t nr = 0;
  837. bs_dst->nr = bs_src->nr;
  838. if (!bs_src->nr)
  839. return;
  840. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  841. memcpy(&bs_dst->entries[0],
  842. &bs_src->entries[ptq->last_branch_pos],
  843. sizeof(struct branch_entry) * nr);
  844. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  845. memcpy(&bs_dst->entries[nr],
  846. &bs_src->entries[0],
  847. sizeof(struct branch_entry) * ptq->last_branch_pos);
  848. }
  849. }
  850. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  851. {
  852. ptq->last_branch_pos = 0;
  853. ptq->last_branch_rb->nr = 0;
  854. }
  855. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  856. {
  857. const struct intel_pt_state *state = ptq->state;
  858. struct branch_stack *bs = ptq->last_branch_rb;
  859. struct branch_entry *be;
  860. if (!ptq->last_branch_pos)
  861. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  862. ptq->last_branch_pos -= 1;
  863. be = &bs->entries[ptq->last_branch_pos];
  864. be->from = state->from_ip;
  865. be->to = state->to_ip;
  866. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  867. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  868. /* No support for mispredict */
  869. be->flags.mispred = ptq->pt->mispred_all;
  870. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  871. bs->nr += 1;
  872. }
  873. static inline bool intel_pt_skip_event(struct intel_pt *pt)
  874. {
  875. return pt->synth_opts.initial_skip &&
  876. pt->num_events++ < pt->synth_opts.initial_skip;
  877. }
  878. static void intel_pt_prep_b_sample(struct intel_pt *pt,
  879. struct intel_pt_queue *ptq,
  880. union perf_event *event,
  881. struct perf_sample *sample)
  882. {
  883. if (!pt->timeless_decoding)
  884. sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  885. sample->ip = ptq->state->from_ip;
  886. sample->cpumode = intel_pt_cpumode(pt, sample->ip);
  887. sample->pid = ptq->pid;
  888. sample->tid = ptq->tid;
  889. sample->addr = ptq->state->to_ip;
  890. sample->period = 1;
  891. sample->cpu = ptq->cpu;
  892. sample->flags = ptq->flags;
  893. sample->insn_len = ptq->insn_len;
  894. memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
  895. event->sample.header.type = PERF_RECORD_SAMPLE;
  896. event->sample.header.misc = sample->cpumode;
  897. event->sample.header.size = sizeof(struct perf_event_header);
  898. }
  899. static int intel_pt_inject_event(union perf_event *event,
  900. struct perf_sample *sample, u64 type)
  901. {
  902. event->header.size = perf_event__sample_event_size(sample, type, 0);
  903. return perf_event__synthesize_sample(event, type, 0, sample);
  904. }
  905. static inline int intel_pt_opt_inject(struct intel_pt *pt,
  906. union perf_event *event,
  907. struct perf_sample *sample, u64 type)
  908. {
  909. if (!pt->synth_opts.inject)
  910. return 0;
  911. return intel_pt_inject_event(event, sample, type);
  912. }
  913. static int intel_pt_deliver_synth_b_event(struct intel_pt *pt,
  914. union perf_event *event,
  915. struct perf_sample *sample, u64 type)
  916. {
  917. int ret;
  918. ret = intel_pt_opt_inject(pt, event, sample, type);
  919. if (ret)
  920. return ret;
  921. ret = perf_session__deliver_synth_event(pt->session, event, sample);
  922. if (ret)
  923. pr_err("Intel PT: failed to deliver event, error %d\n", ret);
  924. return ret;
  925. }
  926. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  927. {
  928. struct intel_pt *pt = ptq->pt;
  929. union perf_event *event = ptq->event_buf;
  930. struct perf_sample sample = { .ip = 0, };
  931. struct dummy_branch_stack {
  932. u64 nr;
  933. struct branch_entry entries;
  934. } dummy_bs;
  935. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  936. return 0;
  937. if (intel_pt_skip_event(pt))
  938. return 0;
  939. intel_pt_prep_b_sample(pt, ptq, event, &sample);
  940. sample.id = ptq->pt->branches_id;
  941. sample.stream_id = ptq->pt->branches_id;
  942. /*
  943. * perf report cannot handle events without a branch stack when using
  944. * SORT_MODE__BRANCH so make a dummy one.
  945. */
  946. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  947. dummy_bs = (struct dummy_branch_stack){
  948. .nr = 1,
  949. .entries = {
  950. .from = sample.ip,
  951. .to = sample.addr,
  952. },
  953. };
  954. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  955. }
  956. return intel_pt_deliver_synth_b_event(pt, event, &sample,
  957. pt->branches_sample_type);
  958. }
  959. static void intel_pt_prep_sample(struct intel_pt *pt,
  960. struct intel_pt_queue *ptq,
  961. union perf_event *event,
  962. struct perf_sample *sample)
  963. {
  964. intel_pt_prep_b_sample(pt, ptq, event, sample);
  965. if (pt->synth_opts.callchain) {
  966. thread_stack__sample(ptq->thread, ptq->chain,
  967. pt->synth_opts.callchain_sz + 1,
  968. sample->ip, pt->kernel_start);
  969. sample->callchain = ptq->chain;
  970. }
  971. if (pt->synth_opts.last_branch) {
  972. intel_pt_copy_last_branch_rb(ptq);
  973. sample->branch_stack = ptq->last_branch;
  974. }
  975. }
  976. static inline int intel_pt_deliver_synth_event(struct intel_pt *pt,
  977. struct intel_pt_queue *ptq,
  978. union perf_event *event,
  979. struct perf_sample *sample,
  980. u64 type)
  981. {
  982. int ret;
  983. ret = intel_pt_deliver_synth_b_event(pt, event, sample, type);
  984. if (pt->synth_opts.last_branch)
  985. intel_pt_reset_last_branch_rb(ptq);
  986. return ret;
  987. }
  988. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  989. {
  990. struct intel_pt *pt = ptq->pt;
  991. union perf_event *event = ptq->event_buf;
  992. struct perf_sample sample = { .ip = 0, };
  993. if (intel_pt_skip_event(pt))
  994. return 0;
  995. intel_pt_prep_sample(pt, ptq, event, &sample);
  996. sample.id = ptq->pt->instructions_id;
  997. sample.stream_id = ptq->pt->instructions_id;
  998. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  999. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  1000. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1001. pt->instructions_sample_type);
  1002. }
  1003. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  1004. {
  1005. struct intel_pt *pt = ptq->pt;
  1006. union perf_event *event = ptq->event_buf;
  1007. struct perf_sample sample = { .ip = 0, };
  1008. if (intel_pt_skip_event(pt))
  1009. return 0;
  1010. intel_pt_prep_sample(pt, ptq, event, &sample);
  1011. sample.id = ptq->pt->transactions_id;
  1012. sample.stream_id = ptq->pt->transactions_id;
  1013. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1014. pt->transactions_sample_type);
  1015. }
  1016. static void intel_pt_prep_p_sample(struct intel_pt *pt,
  1017. struct intel_pt_queue *ptq,
  1018. union perf_event *event,
  1019. struct perf_sample *sample)
  1020. {
  1021. intel_pt_prep_sample(pt, ptq, event, sample);
  1022. /*
  1023. * Zero IP is used to mean "trace start" but that is not the case for
  1024. * power or PTWRITE events with no IP, so clear the flags.
  1025. */
  1026. if (!sample->ip)
  1027. sample->flags = 0;
  1028. }
  1029. static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
  1030. {
  1031. struct intel_pt *pt = ptq->pt;
  1032. union perf_event *event = ptq->event_buf;
  1033. struct perf_sample sample = { .ip = 0, };
  1034. struct perf_synth_intel_ptwrite raw;
  1035. if (intel_pt_skip_event(pt))
  1036. return 0;
  1037. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1038. sample.id = ptq->pt->ptwrites_id;
  1039. sample.stream_id = ptq->pt->ptwrites_id;
  1040. raw.flags = 0;
  1041. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1042. raw.payload = cpu_to_le64(ptq->state->ptw_payload);
  1043. sample.raw_size = perf_synth__raw_size(raw);
  1044. sample.raw_data = perf_synth__raw_data(&raw);
  1045. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1046. pt->ptwrites_sample_type);
  1047. }
  1048. static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
  1049. {
  1050. struct intel_pt *pt = ptq->pt;
  1051. union perf_event *event = ptq->event_buf;
  1052. struct perf_sample sample = { .ip = 0, };
  1053. struct perf_synth_intel_cbr raw;
  1054. u32 flags;
  1055. if (intel_pt_skip_event(pt))
  1056. return 0;
  1057. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1058. sample.id = ptq->pt->cbr_id;
  1059. sample.stream_id = ptq->pt->cbr_id;
  1060. flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
  1061. raw.flags = cpu_to_le32(flags);
  1062. raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
  1063. raw.reserved3 = 0;
  1064. sample.raw_size = perf_synth__raw_size(raw);
  1065. sample.raw_data = perf_synth__raw_data(&raw);
  1066. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1067. pt->pwr_events_sample_type);
  1068. }
  1069. static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
  1070. {
  1071. struct intel_pt *pt = ptq->pt;
  1072. union perf_event *event = ptq->event_buf;
  1073. struct perf_sample sample = { .ip = 0, };
  1074. struct perf_synth_intel_mwait raw;
  1075. if (intel_pt_skip_event(pt))
  1076. return 0;
  1077. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1078. sample.id = ptq->pt->mwait_id;
  1079. sample.stream_id = ptq->pt->mwait_id;
  1080. raw.reserved = 0;
  1081. raw.payload = cpu_to_le64(ptq->state->mwait_payload);
  1082. sample.raw_size = perf_synth__raw_size(raw);
  1083. sample.raw_data = perf_synth__raw_data(&raw);
  1084. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1085. pt->pwr_events_sample_type);
  1086. }
  1087. static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
  1088. {
  1089. struct intel_pt *pt = ptq->pt;
  1090. union perf_event *event = ptq->event_buf;
  1091. struct perf_sample sample = { .ip = 0, };
  1092. struct perf_synth_intel_pwre raw;
  1093. if (intel_pt_skip_event(pt))
  1094. return 0;
  1095. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1096. sample.id = ptq->pt->pwre_id;
  1097. sample.stream_id = ptq->pt->pwre_id;
  1098. raw.reserved = 0;
  1099. raw.payload = cpu_to_le64(ptq->state->pwre_payload);
  1100. sample.raw_size = perf_synth__raw_size(raw);
  1101. sample.raw_data = perf_synth__raw_data(&raw);
  1102. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1103. pt->pwr_events_sample_type);
  1104. }
  1105. static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
  1106. {
  1107. struct intel_pt *pt = ptq->pt;
  1108. union perf_event *event = ptq->event_buf;
  1109. struct perf_sample sample = { .ip = 0, };
  1110. struct perf_synth_intel_exstop raw;
  1111. if (intel_pt_skip_event(pt))
  1112. return 0;
  1113. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1114. sample.id = ptq->pt->exstop_id;
  1115. sample.stream_id = ptq->pt->exstop_id;
  1116. raw.flags = 0;
  1117. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1118. sample.raw_size = perf_synth__raw_size(raw);
  1119. sample.raw_data = perf_synth__raw_data(&raw);
  1120. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1121. pt->pwr_events_sample_type);
  1122. }
  1123. static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
  1124. {
  1125. struct intel_pt *pt = ptq->pt;
  1126. union perf_event *event = ptq->event_buf;
  1127. struct perf_sample sample = { .ip = 0, };
  1128. struct perf_synth_intel_pwrx raw;
  1129. if (intel_pt_skip_event(pt))
  1130. return 0;
  1131. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1132. sample.id = ptq->pt->pwrx_id;
  1133. sample.stream_id = ptq->pt->pwrx_id;
  1134. raw.reserved = 0;
  1135. raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
  1136. sample.raw_size = perf_synth__raw_size(raw);
  1137. sample.raw_data = perf_synth__raw_data(&raw);
  1138. return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
  1139. pt->pwr_events_sample_type);
  1140. }
  1141. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  1142. pid_t pid, pid_t tid, u64 ip)
  1143. {
  1144. union perf_event event;
  1145. char msg[MAX_AUXTRACE_ERROR_MSG];
  1146. int err;
  1147. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  1148. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  1149. code, cpu, pid, tid, ip, msg);
  1150. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  1151. if (err)
  1152. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  1153. err);
  1154. return err;
  1155. }
  1156. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  1157. {
  1158. struct auxtrace_queue *queue;
  1159. pid_t tid = ptq->next_tid;
  1160. int err;
  1161. if (tid == -1)
  1162. return 0;
  1163. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  1164. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  1165. queue = &pt->queues.queue_array[ptq->queue_nr];
  1166. intel_pt_set_pid_tid_cpu(pt, queue);
  1167. ptq->next_tid = -1;
  1168. return err;
  1169. }
  1170. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  1171. {
  1172. struct intel_pt *pt = ptq->pt;
  1173. return ip == pt->switch_ip &&
  1174. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  1175. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  1176. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  1177. }
  1178. #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
  1179. INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT | \
  1180. INTEL_PT_CBR_CHG)
  1181. static int intel_pt_sample(struct intel_pt_queue *ptq)
  1182. {
  1183. const struct intel_pt_state *state = ptq->state;
  1184. struct intel_pt *pt = ptq->pt;
  1185. int err;
  1186. if (!ptq->have_sample)
  1187. return 0;
  1188. ptq->have_sample = false;
  1189. if (pt->sample_pwr_events && (state->type & INTEL_PT_PWR_EVT)) {
  1190. if (state->type & INTEL_PT_CBR_CHG) {
  1191. err = intel_pt_synth_cbr_sample(ptq);
  1192. if (err)
  1193. return err;
  1194. }
  1195. if (state->type & INTEL_PT_MWAIT_OP) {
  1196. err = intel_pt_synth_mwait_sample(ptq);
  1197. if (err)
  1198. return err;
  1199. }
  1200. if (state->type & INTEL_PT_PWR_ENTRY) {
  1201. err = intel_pt_synth_pwre_sample(ptq);
  1202. if (err)
  1203. return err;
  1204. }
  1205. if (state->type & INTEL_PT_EX_STOP) {
  1206. err = intel_pt_synth_exstop_sample(ptq);
  1207. if (err)
  1208. return err;
  1209. }
  1210. if (state->type & INTEL_PT_PWR_EXIT) {
  1211. err = intel_pt_synth_pwrx_sample(ptq);
  1212. if (err)
  1213. return err;
  1214. }
  1215. }
  1216. if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
  1217. err = intel_pt_synth_instruction_sample(ptq);
  1218. if (err)
  1219. return err;
  1220. }
  1221. if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
  1222. err = intel_pt_synth_transaction_sample(ptq);
  1223. if (err)
  1224. return err;
  1225. }
  1226. if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
  1227. err = intel_pt_synth_ptwrite_sample(ptq);
  1228. if (err)
  1229. return err;
  1230. }
  1231. if (!(state->type & INTEL_PT_BRANCH))
  1232. return 0;
  1233. if (pt->synth_opts.callchain || pt->synth_opts.thread_stack)
  1234. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1235. state->to_ip, ptq->insn_len,
  1236. state->trace_nr);
  1237. else
  1238. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1239. if (pt->sample_branches) {
  1240. err = intel_pt_synth_branch_sample(ptq);
  1241. if (err)
  1242. return err;
  1243. }
  1244. if (pt->synth_opts.last_branch)
  1245. intel_pt_update_last_branch_rb(ptq);
  1246. if (!ptq->sync_switch)
  1247. return 0;
  1248. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1249. switch (ptq->switch_state) {
  1250. case INTEL_PT_SS_NOT_TRACING:
  1251. case INTEL_PT_SS_UNKNOWN:
  1252. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1253. err = intel_pt_next_tid(pt, ptq);
  1254. if (err)
  1255. return err;
  1256. ptq->switch_state = INTEL_PT_SS_TRACING;
  1257. break;
  1258. default:
  1259. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1260. return 1;
  1261. }
  1262. } else if (!state->to_ip) {
  1263. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1264. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1265. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1266. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1267. state->to_ip == pt->ptss_ip &&
  1268. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1269. ptq->switch_state = INTEL_PT_SS_TRACING;
  1270. }
  1271. return 0;
  1272. }
  1273. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1274. {
  1275. struct machine *machine = pt->machine;
  1276. struct map *map;
  1277. struct symbol *sym, *start;
  1278. u64 ip, switch_ip = 0;
  1279. const char *ptss;
  1280. if (ptss_ip)
  1281. *ptss_ip = 0;
  1282. map = machine__kernel_map(machine);
  1283. if (!map)
  1284. return 0;
  1285. if (map__load(map))
  1286. return 0;
  1287. start = dso__first_symbol(map->dso);
  1288. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1289. if (sym->binding == STB_GLOBAL &&
  1290. !strcmp(sym->name, "__switch_to")) {
  1291. ip = map->unmap_ip(map, sym->start);
  1292. if (ip >= map->start && ip < map->end) {
  1293. switch_ip = ip;
  1294. break;
  1295. }
  1296. }
  1297. }
  1298. if (!switch_ip || !ptss_ip)
  1299. return 0;
  1300. if (pt->have_sched_switch == 1)
  1301. ptss = "perf_trace_sched_switch";
  1302. else
  1303. ptss = "__perf_event_task_sched_out";
  1304. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1305. if (!strcmp(sym->name, ptss)) {
  1306. ip = map->unmap_ip(map, sym->start);
  1307. if (ip >= map->start && ip < map->end) {
  1308. *ptss_ip = ip;
  1309. break;
  1310. }
  1311. }
  1312. }
  1313. return switch_ip;
  1314. }
  1315. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1316. {
  1317. unsigned int i;
  1318. pt->sync_switch = true;
  1319. for (i = 0; i < pt->queues.nr_queues; i++) {
  1320. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1321. struct intel_pt_queue *ptq = queue->priv;
  1322. if (ptq)
  1323. ptq->sync_switch = true;
  1324. }
  1325. }
  1326. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1327. {
  1328. const struct intel_pt_state *state = ptq->state;
  1329. struct intel_pt *pt = ptq->pt;
  1330. int err;
  1331. if (!pt->kernel_start) {
  1332. pt->kernel_start = machine__kernel_start(pt->machine);
  1333. if (pt->per_cpu_mmaps &&
  1334. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1335. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1336. !pt->sampling_mode) {
  1337. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1338. if (pt->switch_ip) {
  1339. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1340. pt->switch_ip, pt->ptss_ip);
  1341. intel_pt_enable_sync_switch(pt);
  1342. }
  1343. }
  1344. }
  1345. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1346. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1347. while (1) {
  1348. err = intel_pt_sample(ptq);
  1349. if (err)
  1350. return err;
  1351. state = intel_pt_decode(ptq->decoder);
  1352. if (state->err) {
  1353. if (state->err == INTEL_PT_ERR_NODATA)
  1354. return 1;
  1355. if (ptq->sync_switch &&
  1356. state->from_ip >= pt->kernel_start) {
  1357. ptq->sync_switch = false;
  1358. intel_pt_next_tid(pt, ptq);
  1359. }
  1360. if (pt->synth_opts.errors) {
  1361. err = intel_pt_synth_error(pt, state->err,
  1362. ptq->cpu, ptq->pid,
  1363. ptq->tid,
  1364. state->from_ip);
  1365. if (err)
  1366. return err;
  1367. }
  1368. continue;
  1369. }
  1370. ptq->state = state;
  1371. ptq->have_sample = true;
  1372. intel_pt_sample_flags(ptq);
  1373. /* Use estimated TSC upon return to user space */
  1374. if (pt->est_tsc &&
  1375. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1376. state->to_ip && state->to_ip < pt->kernel_start) {
  1377. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1378. state->timestamp, state->est_timestamp);
  1379. ptq->timestamp = state->est_timestamp;
  1380. /* Use estimated TSC in unknown switch state */
  1381. } else if (ptq->sync_switch &&
  1382. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1383. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1384. ptq->next_tid == -1) {
  1385. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1386. state->timestamp, state->est_timestamp);
  1387. ptq->timestamp = state->est_timestamp;
  1388. } else if (state->timestamp > ptq->timestamp) {
  1389. ptq->timestamp = state->timestamp;
  1390. }
  1391. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1392. *timestamp = ptq->timestamp;
  1393. return 0;
  1394. }
  1395. }
  1396. return 0;
  1397. }
  1398. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1399. {
  1400. if (pt->queues.new_data) {
  1401. pt->queues.new_data = false;
  1402. return intel_pt_setup_queues(pt);
  1403. }
  1404. return 0;
  1405. }
  1406. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1407. {
  1408. unsigned int queue_nr;
  1409. u64 ts;
  1410. int ret;
  1411. while (1) {
  1412. struct auxtrace_queue *queue;
  1413. struct intel_pt_queue *ptq;
  1414. if (!pt->heap.heap_cnt)
  1415. return 0;
  1416. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1417. return 0;
  1418. queue_nr = pt->heap.heap_array[0].queue_nr;
  1419. queue = &pt->queues.queue_array[queue_nr];
  1420. ptq = queue->priv;
  1421. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1422. queue_nr, pt->heap.heap_array[0].ordinal,
  1423. timestamp);
  1424. auxtrace_heap__pop(&pt->heap);
  1425. if (pt->heap.heap_cnt) {
  1426. ts = pt->heap.heap_array[0].ordinal + 1;
  1427. if (ts > timestamp)
  1428. ts = timestamp;
  1429. } else {
  1430. ts = timestamp;
  1431. }
  1432. intel_pt_set_pid_tid_cpu(pt, queue);
  1433. ret = intel_pt_run_decoder(ptq, &ts);
  1434. if (ret < 0) {
  1435. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1436. return ret;
  1437. }
  1438. if (!ret) {
  1439. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1440. if (ret < 0)
  1441. return ret;
  1442. } else {
  1443. ptq->on_heap = false;
  1444. }
  1445. }
  1446. return 0;
  1447. }
  1448. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1449. u64 time_)
  1450. {
  1451. struct auxtrace_queues *queues = &pt->queues;
  1452. unsigned int i;
  1453. u64 ts = 0;
  1454. for (i = 0; i < queues->nr_queues; i++) {
  1455. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1456. struct intel_pt_queue *ptq = queue->priv;
  1457. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1458. ptq->time = time_;
  1459. intel_pt_set_pid_tid_cpu(pt, queue);
  1460. intel_pt_run_decoder(ptq, &ts);
  1461. }
  1462. }
  1463. return 0;
  1464. }
  1465. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1466. {
  1467. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1468. sample->pid, sample->tid, 0);
  1469. }
  1470. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1471. {
  1472. unsigned i, j;
  1473. if (cpu < 0 || !pt->queues.nr_queues)
  1474. return NULL;
  1475. if ((unsigned)cpu >= pt->queues.nr_queues)
  1476. i = pt->queues.nr_queues - 1;
  1477. else
  1478. i = cpu;
  1479. if (pt->queues.queue_array[i].cpu == cpu)
  1480. return pt->queues.queue_array[i].priv;
  1481. for (j = 0; i > 0; j++) {
  1482. if (pt->queues.queue_array[--i].cpu == cpu)
  1483. return pt->queues.queue_array[i].priv;
  1484. }
  1485. for (; j < pt->queues.nr_queues; j++) {
  1486. if (pt->queues.queue_array[j].cpu == cpu)
  1487. return pt->queues.queue_array[j].priv;
  1488. }
  1489. return NULL;
  1490. }
  1491. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1492. u64 timestamp)
  1493. {
  1494. struct intel_pt_queue *ptq;
  1495. int err;
  1496. if (!pt->sync_switch)
  1497. return 1;
  1498. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1499. if (!ptq || !ptq->sync_switch)
  1500. return 1;
  1501. switch (ptq->switch_state) {
  1502. case INTEL_PT_SS_NOT_TRACING:
  1503. ptq->next_tid = -1;
  1504. break;
  1505. case INTEL_PT_SS_UNKNOWN:
  1506. case INTEL_PT_SS_TRACING:
  1507. ptq->next_tid = tid;
  1508. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1509. return 0;
  1510. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1511. if (!ptq->on_heap) {
  1512. ptq->timestamp = perf_time_to_tsc(timestamp,
  1513. &pt->tc);
  1514. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1515. ptq->timestamp);
  1516. if (err)
  1517. return err;
  1518. ptq->on_heap = true;
  1519. }
  1520. ptq->switch_state = INTEL_PT_SS_TRACING;
  1521. break;
  1522. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1523. ptq->next_tid = tid;
  1524. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1525. break;
  1526. default:
  1527. break;
  1528. }
  1529. return 1;
  1530. }
  1531. static int intel_pt_process_switch(struct intel_pt *pt,
  1532. struct perf_sample *sample)
  1533. {
  1534. struct perf_evsel *evsel;
  1535. pid_t tid;
  1536. int cpu, ret;
  1537. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1538. if (evsel != pt->switch_evsel)
  1539. return 0;
  1540. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1541. cpu = sample->cpu;
  1542. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1543. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1544. &pt->tc));
  1545. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1546. if (ret <= 0)
  1547. return ret;
  1548. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1549. }
  1550. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1551. struct perf_sample *sample)
  1552. {
  1553. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1554. pid_t pid, tid;
  1555. int cpu, ret;
  1556. cpu = sample->cpu;
  1557. if (pt->have_sched_switch == 3) {
  1558. if (!out)
  1559. return 0;
  1560. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1561. pr_err("Expecting CPU-wide context switch event\n");
  1562. return -EINVAL;
  1563. }
  1564. pid = event->context_switch.next_prev_pid;
  1565. tid = event->context_switch.next_prev_tid;
  1566. } else {
  1567. if (out)
  1568. return 0;
  1569. pid = sample->pid;
  1570. tid = sample->tid;
  1571. }
  1572. if (tid == -1)
  1573. intel_pt_log("context_switch event has no tid\n");
  1574. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1575. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1576. &pt->tc));
  1577. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1578. if (ret <= 0)
  1579. return ret;
  1580. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1581. }
  1582. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1583. union perf_event *event,
  1584. struct perf_sample *sample)
  1585. {
  1586. if (!pt->per_cpu_mmaps)
  1587. return 0;
  1588. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1589. sample->cpu, event->itrace_start.pid,
  1590. event->itrace_start.tid, sample->time,
  1591. perf_time_to_tsc(sample->time, &pt->tc));
  1592. return machine__set_current_tid(pt->machine, sample->cpu,
  1593. event->itrace_start.pid,
  1594. event->itrace_start.tid);
  1595. }
  1596. static int intel_pt_process_event(struct perf_session *session,
  1597. union perf_event *event,
  1598. struct perf_sample *sample,
  1599. struct perf_tool *tool)
  1600. {
  1601. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1602. auxtrace);
  1603. u64 timestamp;
  1604. int err = 0;
  1605. if (dump_trace)
  1606. return 0;
  1607. if (!tool->ordered_events) {
  1608. pr_err("Intel Processor Trace requires ordered events\n");
  1609. return -EINVAL;
  1610. }
  1611. if (sample->time && sample->time != (u64)-1)
  1612. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1613. else
  1614. timestamp = 0;
  1615. if (timestamp || pt->timeless_decoding) {
  1616. err = intel_pt_update_queues(pt);
  1617. if (err)
  1618. return err;
  1619. }
  1620. if (pt->timeless_decoding) {
  1621. if (event->header.type == PERF_RECORD_EXIT) {
  1622. err = intel_pt_process_timeless_queues(pt,
  1623. event->fork.tid,
  1624. sample->time);
  1625. }
  1626. } else if (timestamp) {
  1627. err = intel_pt_process_queues(pt, timestamp);
  1628. }
  1629. if (err)
  1630. return err;
  1631. if (event->header.type == PERF_RECORD_AUX &&
  1632. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1633. pt->synth_opts.errors) {
  1634. err = intel_pt_lost(pt, sample);
  1635. if (err)
  1636. return err;
  1637. }
  1638. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1639. err = intel_pt_process_switch(pt, sample);
  1640. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1641. err = intel_pt_process_itrace_start(pt, event, sample);
  1642. else if (event->header.type == PERF_RECORD_SWITCH ||
  1643. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1644. err = intel_pt_context_switch(pt, event, sample);
  1645. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1646. perf_event__name(event->header.type), event->header.type,
  1647. sample->cpu, sample->time, timestamp);
  1648. return err;
  1649. }
  1650. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1651. {
  1652. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1653. auxtrace);
  1654. int ret;
  1655. if (dump_trace)
  1656. return 0;
  1657. if (!tool->ordered_events)
  1658. return -EINVAL;
  1659. ret = intel_pt_update_queues(pt);
  1660. if (ret < 0)
  1661. return ret;
  1662. if (pt->timeless_decoding)
  1663. return intel_pt_process_timeless_queues(pt, -1,
  1664. MAX_TIMESTAMP - 1);
  1665. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1666. }
  1667. static void intel_pt_free_events(struct perf_session *session)
  1668. {
  1669. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1670. auxtrace);
  1671. struct auxtrace_queues *queues = &pt->queues;
  1672. unsigned int i;
  1673. for (i = 0; i < queues->nr_queues; i++) {
  1674. intel_pt_free_queue(queues->queue_array[i].priv);
  1675. queues->queue_array[i].priv = NULL;
  1676. }
  1677. intel_pt_log_disable();
  1678. auxtrace_queues__free(queues);
  1679. }
  1680. static void intel_pt_free(struct perf_session *session)
  1681. {
  1682. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1683. auxtrace);
  1684. auxtrace_heap__free(&pt->heap);
  1685. intel_pt_free_events(session);
  1686. session->auxtrace = NULL;
  1687. thread__put(pt->unknown_thread);
  1688. addr_filters__exit(&pt->filts);
  1689. zfree(&pt->filter);
  1690. free(pt);
  1691. }
  1692. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1693. union perf_event *event,
  1694. struct perf_tool *tool __maybe_unused)
  1695. {
  1696. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1697. auxtrace);
  1698. if (!pt->data_queued) {
  1699. struct auxtrace_buffer *buffer;
  1700. off_t data_offset;
  1701. int fd = perf_data__fd(session->data);
  1702. int err;
  1703. if (perf_data__is_pipe(session->data)) {
  1704. data_offset = 0;
  1705. } else {
  1706. data_offset = lseek(fd, 0, SEEK_CUR);
  1707. if (data_offset == -1)
  1708. return -errno;
  1709. }
  1710. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1711. data_offset, &buffer);
  1712. if (err)
  1713. return err;
  1714. /* Dump here now we have copied a piped trace out of the pipe */
  1715. if (dump_trace) {
  1716. if (auxtrace_buffer__get_data(buffer, fd)) {
  1717. intel_pt_dump_event(pt, buffer->data,
  1718. buffer->size);
  1719. auxtrace_buffer__put_data(buffer);
  1720. }
  1721. }
  1722. }
  1723. return 0;
  1724. }
  1725. struct intel_pt_synth {
  1726. struct perf_tool dummy_tool;
  1727. struct perf_session *session;
  1728. };
  1729. static int intel_pt_event_synth(struct perf_tool *tool,
  1730. union perf_event *event,
  1731. struct perf_sample *sample __maybe_unused,
  1732. struct machine *machine __maybe_unused)
  1733. {
  1734. struct intel_pt_synth *intel_pt_synth =
  1735. container_of(tool, struct intel_pt_synth, dummy_tool);
  1736. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1737. NULL);
  1738. }
  1739. static int intel_pt_synth_event(struct perf_session *session, const char *name,
  1740. struct perf_event_attr *attr, u64 id)
  1741. {
  1742. struct intel_pt_synth intel_pt_synth;
  1743. int err;
  1744. pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1745. name, id, (u64)attr->sample_type);
  1746. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1747. intel_pt_synth.session = session;
  1748. err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1749. &id, intel_pt_event_synth);
  1750. if (err)
  1751. pr_err("%s: failed to synthesize '%s' event type\n",
  1752. __func__, name);
  1753. return err;
  1754. }
  1755. static void intel_pt_set_event_name(struct perf_evlist *evlist, u64 id,
  1756. const char *name)
  1757. {
  1758. struct perf_evsel *evsel;
  1759. evlist__for_each_entry(evlist, evsel) {
  1760. if (evsel->id && evsel->id[0] == id) {
  1761. if (evsel->name)
  1762. zfree(&evsel->name);
  1763. evsel->name = strdup(name);
  1764. break;
  1765. }
  1766. }
  1767. }
  1768. static struct perf_evsel *intel_pt_evsel(struct intel_pt *pt,
  1769. struct perf_evlist *evlist)
  1770. {
  1771. struct perf_evsel *evsel;
  1772. evlist__for_each_entry(evlist, evsel) {
  1773. if (evsel->attr.type == pt->pmu_type && evsel->ids)
  1774. return evsel;
  1775. }
  1776. return NULL;
  1777. }
  1778. static int intel_pt_synth_events(struct intel_pt *pt,
  1779. struct perf_session *session)
  1780. {
  1781. struct perf_evlist *evlist = session->evlist;
  1782. struct perf_evsel *evsel = intel_pt_evsel(pt, evlist);
  1783. struct perf_event_attr attr;
  1784. u64 id;
  1785. int err;
  1786. if (!evsel) {
  1787. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1788. return 0;
  1789. }
  1790. memset(&attr, 0, sizeof(struct perf_event_attr));
  1791. attr.size = sizeof(struct perf_event_attr);
  1792. attr.type = PERF_TYPE_HARDWARE;
  1793. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1794. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1795. PERF_SAMPLE_PERIOD;
  1796. if (pt->timeless_decoding)
  1797. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1798. else
  1799. attr.sample_type |= PERF_SAMPLE_TIME;
  1800. if (!pt->per_cpu_mmaps)
  1801. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1802. attr.exclude_user = evsel->attr.exclude_user;
  1803. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1804. attr.exclude_hv = evsel->attr.exclude_hv;
  1805. attr.exclude_host = evsel->attr.exclude_host;
  1806. attr.exclude_guest = evsel->attr.exclude_guest;
  1807. attr.sample_id_all = evsel->attr.sample_id_all;
  1808. attr.read_format = evsel->attr.read_format;
  1809. id = evsel->id[0] + 1000000000;
  1810. if (!id)
  1811. id = 1;
  1812. if (pt->synth_opts.branches) {
  1813. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1814. attr.sample_period = 1;
  1815. attr.sample_type |= PERF_SAMPLE_ADDR;
  1816. err = intel_pt_synth_event(session, "branches", &attr, id);
  1817. if (err)
  1818. return err;
  1819. pt->sample_branches = true;
  1820. pt->branches_sample_type = attr.sample_type;
  1821. pt->branches_id = id;
  1822. id += 1;
  1823. attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
  1824. }
  1825. if (pt->synth_opts.callchain)
  1826. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1827. if (pt->synth_opts.last_branch)
  1828. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1829. if (pt->synth_opts.instructions) {
  1830. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1831. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1832. attr.sample_period =
  1833. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1834. else
  1835. attr.sample_period = pt->synth_opts.period;
  1836. err = intel_pt_synth_event(session, "instructions", &attr, id);
  1837. if (err)
  1838. return err;
  1839. pt->sample_instructions = true;
  1840. pt->instructions_sample_type = attr.sample_type;
  1841. pt->instructions_id = id;
  1842. id += 1;
  1843. }
  1844. attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
  1845. attr.sample_period = 1;
  1846. if (pt->synth_opts.transactions) {
  1847. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1848. err = intel_pt_synth_event(session, "transactions", &attr, id);
  1849. if (err)
  1850. return err;
  1851. pt->sample_transactions = true;
  1852. pt->transactions_sample_type = attr.sample_type;
  1853. pt->transactions_id = id;
  1854. intel_pt_set_event_name(evlist, id, "transactions");
  1855. id += 1;
  1856. }
  1857. attr.type = PERF_TYPE_SYNTH;
  1858. attr.sample_type |= PERF_SAMPLE_RAW;
  1859. if (pt->synth_opts.ptwrites) {
  1860. attr.config = PERF_SYNTH_INTEL_PTWRITE;
  1861. err = intel_pt_synth_event(session, "ptwrite", &attr, id);
  1862. if (err)
  1863. return err;
  1864. pt->sample_ptwrites = true;
  1865. pt->ptwrites_sample_type = attr.sample_type;
  1866. pt->ptwrites_id = id;
  1867. intel_pt_set_event_name(evlist, id, "ptwrite");
  1868. id += 1;
  1869. }
  1870. if (pt->synth_opts.pwr_events) {
  1871. pt->sample_pwr_events = true;
  1872. pt->pwr_events_sample_type = attr.sample_type;
  1873. attr.config = PERF_SYNTH_INTEL_CBR;
  1874. err = intel_pt_synth_event(session, "cbr", &attr, id);
  1875. if (err)
  1876. return err;
  1877. pt->cbr_id = id;
  1878. intel_pt_set_event_name(evlist, id, "cbr");
  1879. id += 1;
  1880. }
  1881. if (pt->synth_opts.pwr_events && (evsel->attr.config & 0x10)) {
  1882. attr.config = PERF_SYNTH_INTEL_MWAIT;
  1883. err = intel_pt_synth_event(session, "mwait", &attr, id);
  1884. if (err)
  1885. return err;
  1886. pt->mwait_id = id;
  1887. intel_pt_set_event_name(evlist, id, "mwait");
  1888. id += 1;
  1889. attr.config = PERF_SYNTH_INTEL_PWRE;
  1890. err = intel_pt_synth_event(session, "pwre", &attr, id);
  1891. if (err)
  1892. return err;
  1893. pt->pwre_id = id;
  1894. intel_pt_set_event_name(evlist, id, "pwre");
  1895. id += 1;
  1896. attr.config = PERF_SYNTH_INTEL_EXSTOP;
  1897. err = intel_pt_synth_event(session, "exstop", &attr, id);
  1898. if (err)
  1899. return err;
  1900. pt->exstop_id = id;
  1901. intel_pt_set_event_name(evlist, id, "exstop");
  1902. id += 1;
  1903. attr.config = PERF_SYNTH_INTEL_PWRX;
  1904. err = intel_pt_synth_event(session, "pwrx", &attr, id);
  1905. if (err)
  1906. return err;
  1907. pt->pwrx_id = id;
  1908. intel_pt_set_event_name(evlist, id, "pwrx");
  1909. id += 1;
  1910. }
  1911. return 0;
  1912. }
  1913. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1914. {
  1915. struct perf_evsel *evsel;
  1916. evlist__for_each_entry_reverse(evlist, evsel) {
  1917. const char *name = perf_evsel__name(evsel);
  1918. if (!strcmp(name, "sched:sched_switch"))
  1919. return evsel;
  1920. }
  1921. return NULL;
  1922. }
  1923. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1924. {
  1925. struct perf_evsel *evsel;
  1926. evlist__for_each_entry(evlist, evsel) {
  1927. if (evsel->attr.context_switch)
  1928. return true;
  1929. }
  1930. return false;
  1931. }
  1932. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1933. {
  1934. struct intel_pt *pt = data;
  1935. if (!strcmp(var, "intel-pt.mispred-all"))
  1936. pt->mispred_all = perf_config_bool(var, value);
  1937. return 0;
  1938. }
  1939. static const char * const intel_pt_info_fmts[] = {
  1940. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1941. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1942. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1943. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1944. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1945. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1946. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1947. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1948. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1949. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1950. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1951. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1952. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1953. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1954. [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
  1955. [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
  1956. };
  1957. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1958. {
  1959. int i;
  1960. if (!dump_trace)
  1961. return;
  1962. for (i = start; i <= finish; i++)
  1963. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1964. }
  1965. static void intel_pt_print_info_str(const char *name, const char *str)
  1966. {
  1967. if (!dump_trace)
  1968. return;
  1969. fprintf(stdout, " %-20s%s\n", name, str ? str : "");
  1970. }
  1971. static bool intel_pt_has(struct auxtrace_info_event *auxtrace_info, int pos)
  1972. {
  1973. return auxtrace_info->header.size >=
  1974. sizeof(struct auxtrace_info_event) + (sizeof(u64) * (pos + 1));
  1975. }
  1976. int intel_pt_process_auxtrace_info(union perf_event *event,
  1977. struct perf_session *session)
  1978. {
  1979. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1980. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1981. struct intel_pt *pt;
  1982. void *info_end;
  1983. u64 *info;
  1984. int err;
  1985. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1986. min_sz)
  1987. return -EINVAL;
  1988. pt = zalloc(sizeof(struct intel_pt));
  1989. if (!pt)
  1990. return -ENOMEM;
  1991. addr_filters__init(&pt->filts);
  1992. err = perf_config(intel_pt_perf_config, pt);
  1993. if (err)
  1994. goto err_free;
  1995. err = auxtrace_queues__init(&pt->queues);
  1996. if (err)
  1997. goto err_free;
  1998. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1999. pt->session = session;
  2000. pt->machine = &session->machines.host; /* No kvm support */
  2001. pt->auxtrace_type = auxtrace_info->type;
  2002. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  2003. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  2004. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  2005. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  2006. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  2007. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  2008. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  2009. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  2010. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  2011. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  2012. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  2013. INTEL_PT_PER_CPU_MMAPS);
  2014. if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
  2015. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  2016. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  2017. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  2018. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  2019. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  2020. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  2021. INTEL_PT_CYC_BIT);
  2022. }
  2023. if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
  2024. pt->max_non_turbo_ratio =
  2025. auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
  2026. intel_pt_print_info(&auxtrace_info->priv[0],
  2027. INTEL_PT_MAX_NONTURBO_RATIO,
  2028. INTEL_PT_MAX_NONTURBO_RATIO);
  2029. }
  2030. info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
  2031. info_end = (void *)info + auxtrace_info->header.size;
  2032. if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
  2033. size_t len;
  2034. len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
  2035. intel_pt_print_info(&auxtrace_info->priv[0],
  2036. INTEL_PT_FILTER_STR_LEN,
  2037. INTEL_PT_FILTER_STR_LEN);
  2038. if (len) {
  2039. const char *filter = (const char *)info;
  2040. len = roundup(len + 1, 8);
  2041. info += len >> 3;
  2042. if ((void *)info > info_end) {
  2043. pr_err("%s: bad filter string length\n", __func__);
  2044. err = -EINVAL;
  2045. goto err_free_queues;
  2046. }
  2047. pt->filter = memdup(filter, len);
  2048. if (!pt->filter) {
  2049. err = -ENOMEM;
  2050. goto err_free_queues;
  2051. }
  2052. if (session->header.needs_swap)
  2053. mem_bswap_64(pt->filter, len);
  2054. if (pt->filter[len - 1]) {
  2055. pr_err("%s: filter string not null terminated\n", __func__);
  2056. err = -EINVAL;
  2057. goto err_free_queues;
  2058. }
  2059. err = addr_filters__parse_bare_filter(&pt->filts,
  2060. filter);
  2061. if (err)
  2062. goto err_free_queues;
  2063. }
  2064. intel_pt_print_info_str("Filter string", pt->filter);
  2065. }
  2066. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  2067. if (pt->timeless_decoding && !pt->tc.time_mult)
  2068. pt->tc.time_mult = 1;
  2069. pt->have_tsc = intel_pt_have_tsc(pt);
  2070. pt->sampling_mode = false;
  2071. pt->est_tsc = !pt->timeless_decoding;
  2072. pt->unknown_thread = thread__new(999999999, 999999999);
  2073. if (!pt->unknown_thread) {
  2074. err = -ENOMEM;
  2075. goto err_free_queues;
  2076. }
  2077. /*
  2078. * Since this thread will not be kept in any rbtree not in a
  2079. * list, initialize its list node so that at thread__put() the
  2080. * current thread lifetime assuption is kept and we don't segfault
  2081. * at list_del_init().
  2082. */
  2083. INIT_LIST_HEAD(&pt->unknown_thread->node);
  2084. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  2085. if (err)
  2086. goto err_delete_thread;
  2087. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  2088. err = -ENOMEM;
  2089. goto err_delete_thread;
  2090. }
  2091. pt->auxtrace.process_event = intel_pt_process_event;
  2092. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  2093. pt->auxtrace.flush_events = intel_pt_flush;
  2094. pt->auxtrace.free_events = intel_pt_free_events;
  2095. pt->auxtrace.free = intel_pt_free;
  2096. session->auxtrace = &pt->auxtrace;
  2097. if (dump_trace)
  2098. return 0;
  2099. if (pt->have_sched_switch == 1) {
  2100. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  2101. if (!pt->switch_evsel) {
  2102. pr_err("%s: missing sched_switch event\n", __func__);
  2103. err = -EINVAL;
  2104. goto err_delete_thread;
  2105. }
  2106. } else if (pt->have_sched_switch == 2 &&
  2107. !intel_pt_find_switch(session->evlist)) {
  2108. pr_err("%s: missing context_switch attribute flag\n", __func__);
  2109. err = -EINVAL;
  2110. goto err_delete_thread;
  2111. }
  2112. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  2113. pt->synth_opts = *session->itrace_synth_opts;
  2114. } else {
  2115. itrace_synth_opts__set_default(&pt->synth_opts);
  2116. if (use_browser != -1) {
  2117. pt->synth_opts.branches = false;
  2118. pt->synth_opts.callchain = true;
  2119. }
  2120. if (session->itrace_synth_opts)
  2121. pt->synth_opts.thread_stack =
  2122. session->itrace_synth_opts->thread_stack;
  2123. }
  2124. if (pt->synth_opts.log)
  2125. intel_pt_log_enable();
  2126. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  2127. if (pt->tc.time_mult) {
  2128. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  2129. if (!pt->max_non_turbo_ratio)
  2130. pt->max_non_turbo_ratio =
  2131. (tsc_freq + 50000000) / 100000000;
  2132. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  2133. intel_pt_log("Maximum non-turbo ratio %u\n",
  2134. pt->max_non_turbo_ratio);
  2135. pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
  2136. }
  2137. if (pt->synth_opts.calls)
  2138. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  2139. PERF_IP_FLAG_TRACE_END;
  2140. if (pt->synth_opts.returns)
  2141. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  2142. PERF_IP_FLAG_TRACE_BEGIN;
  2143. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  2144. symbol_conf.use_callchain = true;
  2145. if (callchain_register_param(&callchain_param) < 0) {
  2146. symbol_conf.use_callchain = false;
  2147. pt->synth_opts.callchain = false;
  2148. }
  2149. }
  2150. err = intel_pt_synth_events(pt, session);
  2151. if (err)
  2152. goto err_delete_thread;
  2153. err = auxtrace_queues__process_index(&pt->queues, session);
  2154. if (err)
  2155. goto err_delete_thread;
  2156. if (pt->queues.populated)
  2157. pt->data_queued = true;
  2158. if (pt->timeless_decoding)
  2159. pr_debug2("Intel PT decoding without timestamps\n");
  2160. return 0;
  2161. err_delete_thread:
  2162. thread__zput(pt->unknown_thread);
  2163. err_free_queues:
  2164. intel_pt_log_disable();
  2165. auxtrace_queues__free(&pt->queues);
  2166. session->auxtrace = NULL;
  2167. err_free:
  2168. addr_filters__exit(&pt->filts);
  2169. zfree(&pt->filter);
  2170. free(pt);
  2171. return err;
  2172. }