speed.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. */
  7. #include <common.h>
  8. #include <asm/processor.h>
  9. #include <asm/immap.h>
  10. #include <asm/io.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /*
  13. * Low Power Divider specifications
  14. */
  15. #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
  16. #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
  17. #define CLOCK_PLL_FVCO_MAX 540000000
  18. #define CLOCK_PLL_FVCO_MIN 300000000
  19. #define CLOCK_PLL_FSYS_MAX 266666666
  20. #define CLOCK_PLL_FSYS_MIN 100000000
  21. #define MHZ 1000000
  22. void clock_enter_limp(int lpdiv)
  23. {
  24. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  25. int i, j;
  26. /* Check bounds of divider */
  27. if (lpdiv < CLOCK_LPD_MIN)
  28. lpdiv = CLOCK_LPD_MIN;
  29. if (lpdiv > CLOCK_LPD_MAX)
  30. lpdiv = CLOCK_LPD_MAX;
  31. /* Round divider down to nearest power of two */
  32. for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
  33. /* Apply the divider to the system clock */
  34. clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
  35. /* Enable Limp Mode */
  36. setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  37. }
  38. /*
  39. * brief Exit Limp mode
  40. * warning The PLL should be set and locked prior to exiting Limp mode
  41. */
  42. void clock_exit_limp(void)
  43. {
  44. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  45. pll_t *pll = (pll_t *)MMAP_PLL;
  46. /* Exit Limp mode */
  47. clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
  48. /* Wait for the PLL to lock */
  49. while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
  50. ;
  51. }
  52. /*
  53. * get_clocks() fills in gd->cpu_clock and gd->bus_clk
  54. */
  55. int get_clocks(void)
  56. {
  57. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  58. pll_t *pll = (pll_t *)MMAP_PLL;
  59. int vco, temp, pcrvalue, pfdr;
  60. u8 bootmode;
  61. pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
  62. pfdr = pcrvalue >> 24;
  63. if (pfdr == 0x1E)
  64. bootmode = 0; /* Normal Mode */
  65. #ifdef CONFIG_CF_SBF
  66. bootmode = 3; /* Serial Mode */
  67. #endif
  68. if (bootmode == 0) {
  69. /* Normal mode */
  70. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  71. if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
  72. /* Default value */
  73. pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
  74. pcrvalue |= 0x1E << 24;
  75. out_be32(&pll->pcr, pcrvalue);
  76. vco =
  77. ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
  78. CONFIG_SYS_INPUT_CLKSRC;
  79. }
  80. gd->arch.vco_clk = vco; /* Vco clock */
  81. } else if (bootmode == 3) {
  82. /* serial mode */
  83. vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  84. gd->arch.vco_clk = vco; /* Vco clock */
  85. }
  86. if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
  87. /* Limp mode */
  88. } else {
  89. gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
  90. temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
  91. gd->cpu_clk = vco / temp; /* cpu clock */
  92. temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  93. gd->arch.flb_clk = vco / temp; /* flexbus clock */
  94. gd->bus_clk = gd->arch.flb_clk;
  95. }
  96. #ifdef CONFIG_SYS_I2C_FSL
  97. gd->arch.i2c1_clk = gd->bus_clk;
  98. #endif
  99. return (0);
  100. }