ebi.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
  4. */
  5. #ifndef __EBI__
  6. #define __EBI__
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include "vct.h"
  10. #define EXT_DEVICE_CHANNEL_3 (0x30000000)
  11. #define EXT_DEVICE_CHANNEL_2 (0x20000000)
  12. #define EXT_DEVICE_CHANNEL_1 (0x10000000)
  13. #define EXT_CPU_ACCESS_ACTIVE (0x00000001)
  14. #define EXT_DMA_ACCESS_ACTIVE (1 << 14)
  15. #define EXT_CPU_IORDY_SL (0x00000001)
  16. #define EBI_CPU_WRITE (1 << 31)
  17. #define EBI_CPU_ID_SHIFT (28)
  18. #define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
  19. /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
  20. #define ADDR_LATCH_ENABLE 0
  21. #define ADDR_ACTIVATION 4
  22. #define CHIP_SELECT_START 8
  23. #define OUTPUT_ENABLE_START 12
  24. #define WAIT_TIME 28
  25. #define READ_DURATION 20
  26. /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
  27. #define OUTPUT_ENABLE_END 0
  28. #define CHIP_SELECT_END 4
  29. #define ADDR_DEACTIVATION 8
  30. #define RECOVER_TIME 12
  31. #define ACK_TIME 20
  32. /* various bits in configuration register EBI_DEV[01]_CONFIG1 */
  33. #define EBI_EXTERNAL_DATA_8 (1 << 8)
  34. #define EBI_EXT_ADDR_SHIFT (1 << 22)
  35. #define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
  36. #define EBI_CHIP_SELECT_1 0x2
  37. #define EBI_CHIP_SELECT_2 0x4
  38. #define EBI_BUSY_EN_RD (1 << 12)
  39. #define DIR_ACCESS_WRITE (1 << 20)
  40. #define DIR_ACCESS_MASK (1 << 20)
  41. /* various bits in configuration register EBI_DEV[01]_CONFIG2 */
  42. #define ADDRESS_INCREMENT_ON 0x0
  43. #define ADDRESS_INCREMENT_OFF 0x100
  44. #define QUEUE_LENGTH_1 0x40
  45. #define QUEUE_LENGTH_2 0x80
  46. #define QUEUE_LENGTH_3 0xC0
  47. #define QUEUE_LENGTH_4 0
  48. #define CPU_TRANSFER_SIZE_32 0
  49. #define CPU_TRANSFER_SIZE_16 0x10
  50. #define CPU_TRANSFER_SIZE_8 0x20
  51. #define READ_ENDIANNESS_ABCD 0
  52. #define READ_ENDIANNESS_DCBA 0x4
  53. #define READ_ENDIANNESS_BADC 0x8
  54. #define READ_ENDIANNESS_CDAB 0xC
  55. #define WRITE_ENDIANNESS_ABCD 0
  56. #define WRITE_ENDIANNESS_DCBA 0x1
  57. #define WRITE_ENDIANNESS_BADC 0x2
  58. #define WRITE_ENDIANNESS_CDAB 0x3
  59. /* various bits in configuration register EBI_CTRL_SIG_ACTLV */
  60. #define IORDY_ACTIVELEVEL_HIGH (1 << 14)
  61. #define ALE_ACTIVELEVEL_HIGH (1 << 8)
  62. /* bits in register EBI_SIG_LEVEL */
  63. #define IORDY_LEVEL_MASK 1
  64. static inline void ebi_wait(void)
  65. {
  66. while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
  67. ; /* wait */
  68. }
  69. #endif