clk-peripheral.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Atmel Corporation
  4. * Wenyou.Yang <wenyou.yang@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <linux/io.h>
  10. #include <mach/at91_pmc.h>
  11. #include "pmc.h"
  12. #define PERIPHERAL_ID_MIN 2
  13. #define PERIPHERAL_ID_MAX 31
  14. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  15. enum periph_clk_type {
  16. CLK_PERIPH_AT91RM9200 = 0,
  17. CLK_PERIPH_AT91SAM9X5,
  18. };
  19. /**
  20. * sam9x5_periph_clk_bind() - for the periph clock driver
  21. * Recursively bind its children as clk devices.
  22. *
  23. * @return: 0 on success, or negative error code on failure
  24. */
  25. static int sam9x5_periph_clk_bind(struct udevice *dev)
  26. {
  27. return at91_clk_sub_device_bind(dev, "periph-clk");
  28. }
  29. static const struct udevice_id sam9x5_periph_clk_match[] = {
  30. {
  31. .compatible = "atmel,at91rm9200-clk-peripheral",
  32. .data = CLK_PERIPH_AT91RM9200,
  33. },
  34. {
  35. .compatible = "atmel,at91sam9x5-clk-peripheral",
  36. .data = CLK_PERIPH_AT91SAM9X5,
  37. },
  38. {}
  39. };
  40. U_BOOT_DRIVER(sam9x5_periph_clk) = {
  41. .name = "sam9x5-periph-clk",
  42. .id = UCLASS_MISC,
  43. .of_match = sam9x5_periph_clk_match,
  44. .bind = sam9x5_periph_clk_bind,
  45. };
  46. /*---------------------------------------------------------*/
  47. static int periph_clk_enable(struct clk *clk)
  48. {
  49. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  50. struct at91_pmc *pmc = plat->reg_base;
  51. enum periph_clk_type clk_type;
  52. void *addr;
  53. if (clk->id < PERIPHERAL_ID_MIN)
  54. return -1;
  55. clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
  56. if (clk_type == CLK_PERIPH_AT91RM9200) {
  57. addr = &pmc->pcer;
  58. if (clk->id > PERIPHERAL_ID_MAX)
  59. addr = &pmc->pcer1;
  60. setbits_le32(addr, PERIPHERAL_MASK(clk->id));
  61. } else {
  62. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  63. setbits_le32(&pmc->pcr,
  64. AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
  65. }
  66. return 0;
  67. }
  68. static ulong periph_get_rate(struct clk *clk)
  69. {
  70. struct udevice *dev;
  71. struct clk clk_dev;
  72. ulong clk_rate;
  73. int ret;
  74. dev = dev_get_parent(clk->dev);
  75. ret = clk_get_by_index(dev, 0, &clk_dev);
  76. if (ret)
  77. return ret;
  78. clk_rate = clk_get_rate(&clk_dev);
  79. clk_free(&clk_dev);
  80. return clk_rate;
  81. }
  82. static struct clk_ops periph_clk_ops = {
  83. .of_xlate = at91_clk_of_xlate,
  84. .enable = periph_clk_enable,
  85. .get_rate = periph_get_rate,
  86. };
  87. U_BOOT_DRIVER(clk_periph) = {
  88. .name = "periph-clk",
  89. .id = UCLASS_CLK,
  90. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  91. .probe = at91_clk_probe,
  92. .ops = &periph_clk_ops,
  93. };