clk-system.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Atmel Corporation
  4. * Wenyou.Yang <wenyou.yang@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <linux/io.h>
  10. #include <mach/at91_pmc.h>
  11. #include "pmc.h"
  12. #define SYSTEM_MAX_ID 31
  13. /**
  14. * at91_system_clk_bind() - for the system clock driver
  15. * Recursively bind its children as clk devices.
  16. *
  17. * @return: 0 on success, or negative error code on failure
  18. */
  19. static int at91_system_clk_bind(struct udevice *dev)
  20. {
  21. return at91_clk_sub_device_bind(dev, "system-clk");
  22. }
  23. static const struct udevice_id at91_system_clk_match[] = {
  24. { .compatible = "atmel,at91rm9200-clk-system" },
  25. {}
  26. };
  27. U_BOOT_DRIVER(at91_system_clk) = {
  28. .name = "at91-system-clk",
  29. .id = UCLASS_MISC,
  30. .of_match = at91_system_clk_match,
  31. .bind = at91_system_clk_bind,
  32. };
  33. /*----------------------------------------------------------*/
  34. static inline int is_pck(int id)
  35. {
  36. return (id >= 8) && (id <= 15);
  37. }
  38. static ulong system_clk_get_rate(struct clk *clk)
  39. {
  40. struct clk clk_dev;
  41. int ret;
  42. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  43. if (ret)
  44. return -EINVAL;
  45. return clk_get_rate(&clk_dev);
  46. }
  47. static ulong system_clk_set_rate(struct clk *clk, ulong rate)
  48. {
  49. struct clk clk_dev;
  50. int ret;
  51. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  52. if (ret)
  53. return -EINVAL;
  54. return clk_set_rate(&clk_dev, rate);
  55. }
  56. static int system_clk_enable(struct clk *clk)
  57. {
  58. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  59. struct at91_pmc *pmc = plat->reg_base;
  60. u32 mask;
  61. if (clk->id > SYSTEM_MAX_ID)
  62. return -EINVAL;
  63. mask = BIT(clk->id);
  64. writel(mask, &pmc->scer);
  65. /**
  66. * For the programmable clocks the Ready status in the PMC
  67. * status register should be checked after enabling.
  68. * For other clocks this is unnecessary.
  69. */
  70. if (!is_pck(clk->id))
  71. return 0;
  72. while (!(readl(&pmc->sr) & mask))
  73. ;
  74. return 0;
  75. }
  76. static struct clk_ops system_clk_ops = {
  77. .of_xlate = at91_clk_of_xlate,
  78. .get_rate = system_clk_get_rate,
  79. .set_rate = system_clk_set_rate,
  80. .enable = system_clk_enable,
  81. };
  82. U_BOOT_DRIVER(system_clk) = {
  83. .name = "system-clk",
  84. .id = UCLASS_CLK,
  85. .probe = at91_clk_probe,
  86. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  87. .ops = &system_clk_ops,
  88. };