clk-uclass.c 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. * Copyright (c) 2016, NVIDIA CORPORATION.
  6. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/read.h>
  13. #include <dt-structs.h>
  14. #include <errno.h>
  15. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  16. {
  17. return (const struct clk_ops *)dev->driver->ops;
  18. }
  19. #if CONFIG_IS_ENABLED(OF_CONTROL)
  20. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  21. int clk_get_by_index_platdata(struct udevice *dev, int index,
  22. struct phandle_1_arg *cells, struct clk *clk)
  23. {
  24. int ret;
  25. if (index != 0)
  26. return -ENOSYS;
  27. ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
  28. if (ret)
  29. return ret;
  30. clk->id = cells[0].arg[0];
  31. return 0;
  32. }
  33. # else
  34. static int clk_of_xlate_default(struct clk *clk,
  35. struct ofnode_phandle_args *args)
  36. {
  37. debug("%s(clk=%p)\n", __func__, clk);
  38. if (args->args_count > 1) {
  39. debug("Invaild args_count: %d\n", args->args_count);
  40. return -EINVAL;
  41. }
  42. if (args->args_count)
  43. clk->id = args->args[0];
  44. else
  45. clk->id = 0;
  46. return 0;
  47. }
  48. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  49. int index, struct clk *clk)
  50. {
  51. int ret;
  52. struct ofnode_phandle_args args;
  53. struct udevice *dev_clk;
  54. const struct clk_ops *ops;
  55. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  56. assert(clk);
  57. clk->dev = NULL;
  58. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  59. index, &args);
  60. if (ret) {
  61. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  62. __func__, ret);
  63. return ret;
  64. }
  65. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
  66. if (ret) {
  67. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  68. __func__, ret);
  69. return ret;
  70. }
  71. clk->dev = dev_clk;
  72. ops = clk_dev_ops(dev_clk);
  73. if (ops->of_xlate)
  74. ret = ops->of_xlate(clk, &args);
  75. else
  76. ret = clk_of_xlate_default(clk, &args);
  77. if (ret) {
  78. debug("of_xlate() failed: %d\n", ret);
  79. return ret;
  80. }
  81. return clk_request(dev_clk, clk);
  82. }
  83. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  84. {
  85. return clk_get_by_indexed_prop(dev, "clocks", index, clk);
  86. }
  87. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  88. {
  89. int i, ret, err, count;
  90. bulk->count = 0;
  91. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  92. if (count < 1)
  93. return count;
  94. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  95. if (!bulk->clks)
  96. return -ENOMEM;
  97. for (i = 0; i < count; i++) {
  98. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  99. if (ret < 0)
  100. goto bulk_get_err;
  101. ++bulk->count;
  102. }
  103. return 0;
  104. bulk_get_err:
  105. err = clk_release_all(bulk->clks, bulk->count);
  106. if (err)
  107. debug("%s: could release all clocks for %p\n",
  108. __func__, dev);
  109. return ret;
  110. }
  111. static int clk_set_default_parents(struct udevice *dev)
  112. {
  113. struct clk clk, parent_clk;
  114. int index;
  115. int num_parents;
  116. int ret;
  117. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  118. "#clock-cells");
  119. if (num_parents < 0) {
  120. debug("%s: could not read assigned-clock-parents for %p\n",
  121. __func__, dev);
  122. return 0;
  123. }
  124. for (index = 0; index < num_parents; index++) {
  125. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  126. index, &parent_clk);
  127. if (ret) {
  128. debug("%s: could not get parent clock %d for %s\n",
  129. __func__, index, dev_read_name(dev));
  130. return ret;
  131. }
  132. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  133. index, &clk);
  134. if (ret) {
  135. debug("%s: could not get assigned clock %d for %s\n",
  136. __func__, index, dev_read_name(dev));
  137. return ret;
  138. }
  139. ret = clk_set_parent(&clk, &parent_clk);
  140. /*
  141. * Not all drivers may support clock-reparenting (as of now).
  142. * Ignore errors due to this.
  143. */
  144. if (ret == -ENOSYS)
  145. continue;
  146. if (ret) {
  147. debug("%s: failed to reparent clock %d for %s\n",
  148. __func__, index, dev_read_name(dev));
  149. return ret;
  150. }
  151. }
  152. return 0;
  153. }
  154. static int clk_set_default_rates(struct udevice *dev)
  155. {
  156. struct clk clk;
  157. int index;
  158. int num_rates;
  159. int size;
  160. int ret = 0;
  161. u32 *rates = NULL;
  162. size = dev_read_size(dev, "assigned-clock-rates");
  163. if (size < 0)
  164. return 0;
  165. num_rates = size / sizeof(u32);
  166. rates = calloc(num_rates, sizeof(u32));
  167. if (!rates)
  168. return -ENOMEM;
  169. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  170. if (ret)
  171. goto fail;
  172. for (index = 0; index < num_rates; index++) {
  173. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  174. index, &clk);
  175. if (ret) {
  176. debug("%s: could not get assigned clock %d for %s\n",
  177. __func__, index, dev_read_name(dev));
  178. continue;
  179. }
  180. ret = clk_set_rate(&clk, rates[index]);
  181. if (ret < 0) {
  182. debug("%s: failed to set rate on clock %d for %s\n",
  183. __func__, index, dev_read_name(dev));
  184. break;
  185. }
  186. }
  187. fail:
  188. free(rates);
  189. return ret;
  190. }
  191. int clk_set_defaults(struct udevice *dev)
  192. {
  193. int ret;
  194. /* If this is running pre-reloc state, don't take any action. */
  195. if (!(gd->flags & GD_FLG_RELOC))
  196. return 0;
  197. debug("%s(%s)\n", __func__, dev_read_name(dev));
  198. ret = clk_set_default_parents(dev);
  199. if (ret)
  200. return ret;
  201. ret = clk_set_default_rates(dev);
  202. if (ret < 0)
  203. return ret;
  204. return 0;
  205. }
  206. # endif /* OF_PLATDATA */
  207. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  208. {
  209. int index;
  210. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  211. clk->dev = NULL;
  212. index = dev_read_stringlist_search(dev, "clock-names", name);
  213. if (index < 0) {
  214. debug("fdt_stringlist_search() failed: %d\n", index);
  215. return index;
  216. }
  217. return clk_get_by_index(dev, index, clk);
  218. }
  219. int clk_release_all(struct clk *clk, int count)
  220. {
  221. int i, ret;
  222. for (i = 0; i < count; i++) {
  223. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  224. /* check if clock has been previously requested */
  225. if (!clk[i].dev)
  226. continue;
  227. ret = clk_disable(&clk[i]);
  228. if (ret && ret != -ENOSYS)
  229. return ret;
  230. ret = clk_free(&clk[i]);
  231. if (ret && ret != -ENOSYS)
  232. return ret;
  233. }
  234. return 0;
  235. }
  236. #endif /* OF_CONTROL */
  237. int clk_request(struct udevice *dev, struct clk *clk)
  238. {
  239. const struct clk_ops *ops = clk_dev_ops(dev);
  240. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  241. clk->dev = dev;
  242. if (!ops->request)
  243. return 0;
  244. return ops->request(clk);
  245. }
  246. int clk_free(struct clk *clk)
  247. {
  248. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  249. debug("%s(clk=%p)\n", __func__, clk);
  250. if (!ops->free)
  251. return 0;
  252. return ops->free(clk);
  253. }
  254. ulong clk_get_rate(struct clk *clk)
  255. {
  256. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  257. debug("%s(clk=%p)\n", __func__, clk);
  258. if (!ops->get_rate)
  259. return -ENOSYS;
  260. return ops->get_rate(clk);
  261. }
  262. ulong clk_set_rate(struct clk *clk, ulong rate)
  263. {
  264. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  265. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  266. if (!ops->set_rate)
  267. return -ENOSYS;
  268. return ops->set_rate(clk, rate);
  269. }
  270. int clk_set_parent(struct clk *clk, struct clk *parent)
  271. {
  272. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  273. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  274. if (!ops->set_parent)
  275. return -ENOSYS;
  276. return ops->set_parent(clk, parent);
  277. }
  278. int clk_enable(struct clk *clk)
  279. {
  280. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  281. debug("%s(clk=%p)\n", __func__, clk);
  282. if (!ops->enable)
  283. return -ENOSYS;
  284. return ops->enable(clk);
  285. }
  286. int clk_enable_bulk(struct clk_bulk *bulk)
  287. {
  288. int i, ret;
  289. for (i = 0; i < bulk->count; i++) {
  290. ret = clk_enable(&bulk->clks[i]);
  291. if (ret < 0 && ret != -ENOSYS)
  292. return ret;
  293. }
  294. return 0;
  295. }
  296. int clk_disable(struct clk *clk)
  297. {
  298. const struct clk_ops *ops = clk_dev_ops(clk->dev);
  299. debug("%s(clk=%p)\n", __func__, clk);
  300. if (!ops->disable)
  301. return -ENOSYS;
  302. return ops->disable(clk);
  303. }
  304. int clk_disable_bulk(struct clk_bulk *bulk)
  305. {
  306. int i, ret;
  307. for (i = 0; i < bulk->count; i++) {
  308. ret = clk_disable(&bulk->clks[i]);
  309. if (ret < 0 && ret != -ENOSYS)
  310. return ret;
  311. }
  312. return 0;
  313. }
  314. UCLASS_DRIVER(clk) = {
  315. .id = UCLASS_CLK,
  316. .name = "clk",
  317. };