tegra-car-clk.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch-tegra/clk_rst.h>
  10. static int tegra_car_clk_request(struct clk *clk)
  11. {
  12. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  13. clk->id);
  14. /*
  15. * Note that the first PERIPH_ID_COUNT clock IDs (where the value
  16. * varies per SoC) are the peripheral clocks, which use a numbering
  17. * scheme that matches HW registers 1:1. There are other clock IDs
  18. * beyond this that are assigned arbitrarily by the Tegra CAR DT
  19. * binding. Due to the implementation of this driver, it currently
  20. * only supports the peripheral IDs.
  21. */
  22. if (clk->id >= PERIPH_ID_COUNT)
  23. return -EINVAL;
  24. return 0;
  25. }
  26. static int tegra_car_clk_free(struct clk *clk)
  27. {
  28. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  29. clk->id);
  30. return 0;
  31. }
  32. static ulong tegra_car_clk_get_rate(struct clk *clk)
  33. {
  34. enum clock_id parent;
  35. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  36. clk->id);
  37. parent = clock_get_periph_parent(clk->id);
  38. return clock_get_periph_rate(clk->id, parent);
  39. }
  40. static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
  41. {
  42. enum clock_id parent;
  43. debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
  44. clk->dev, clk->id);
  45. parent = clock_get_periph_parent(clk->id);
  46. return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
  47. }
  48. static int tegra_car_clk_enable(struct clk *clk)
  49. {
  50. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  51. clk->id);
  52. clock_enable(clk->id);
  53. return 0;
  54. }
  55. static int tegra_car_clk_disable(struct clk *clk)
  56. {
  57. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  58. clk->id);
  59. clock_disable(clk->id);
  60. return 0;
  61. }
  62. static struct clk_ops tegra_car_clk_ops = {
  63. .request = tegra_car_clk_request,
  64. .free = tegra_car_clk_free,
  65. .get_rate = tegra_car_clk_get_rate,
  66. .set_rate = tegra_car_clk_set_rate,
  67. .enable = tegra_car_clk_enable,
  68. .disable = tegra_car_clk_disable,
  69. };
  70. static int tegra_car_clk_probe(struct udevice *dev)
  71. {
  72. debug("%s(dev=%p)\n", __func__, dev);
  73. return 0;
  74. }
  75. U_BOOT_DRIVER(tegra_car_clk) = {
  76. .name = "tegra_car_clk",
  77. .id = UCLASS_CLK,
  78. .probe = tegra_car_clk_probe,
  79. .ops = &tegra_car_clk_ops,
  80. };