tegra186-clk.c 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <misc.h>
  9. #include <asm/arch-tegra/bpmp_abi.h>
  10. static ulong tegra186_clk_get_rate(struct clk *clk)
  11. {
  12. struct mrq_clk_request req;
  13. struct mrq_clk_response resp;
  14. int ret;
  15. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  16. clk->id);
  17. req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
  18. ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
  19. sizeof(resp));
  20. if (ret < 0)
  21. return ret;
  22. return resp.clk_get_rate.rate;
  23. }
  24. static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
  25. {
  26. struct mrq_clk_request req;
  27. struct mrq_clk_response resp;
  28. int ret;
  29. debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
  30. clk->dev, clk->id);
  31. req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
  32. req.clk_set_rate.rate = rate;
  33. ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
  34. sizeof(resp));
  35. if (ret < 0)
  36. return ret;
  37. return resp.clk_set_rate.rate;
  38. }
  39. static int tegra186_clk_en_dis(struct clk *clk,
  40. enum mrq_reset_commands cmd)
  41. {
  42. struct mrq_clk_request req;
  43. struct mrq_clk_response resp;
  44. int ret;
  45. req.cmd_and_id = (cmd << 24) | clk->id;
  46. ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
  47. sizeof(resp));
  48. if (ret < 0)
  49. return ret;
  50. return 0;
  51. }
  52. static int tegra186_clk_enable(struct clk *clk)
  53. {
  54. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  55. clk->id);
  56. return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
  57. }
  58. static int tegra186_clk_disable(struct clk *clk)
  59. {
  60. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  61. clk->id);
  62. return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
  63. }
  64. static struct clk_ops tegra186_clk_ops = {
  65. .get_rate = tegra186_clk_get_rate,
  66. .set_rate = tegra186_clk_set_rate,
  67. .enable = tegra186_clk_enable,
  68. .disable = tegra186_clk_disable,
  69. };
  70. static int tegra186_clk_probe(struct udevice *dev)
  71. {
  72. debug("%s(dev=%p)\n", __func__, dev);
  73. return 0;
  74. }
  75. U_BOOT_DRIVER(tegra186_clk) = {
  76. .name = "tegra186_clk",
  77. .id = UCLASS_CLK,
  78. .probe = tegra186_clk_probe,
  79. .ops = &tegra186_clk_ops,
  80. };