pinctrl-at91-pio4.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO4 pinctrl driver
  4. *
  5. * Copyright (C) 2016 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dm/pinctrl.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <mach/atmel_pio4.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /*
  16. * Warning:
  17. * In order to not introduce confusion between Atmel PIO groups and pinctrl
  18. * framework groups, Atmel PIO groups will be called banks.
  19. */
  20. struct atmel_pio4_platdata {
  21. struct atmel_pio4_port *reg_base;
  22. };
  23. static const struct pinconf_param conf_params[] = {
  24. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  25. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
  26. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
  27. { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
  28. { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
  29. { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
  30. { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
  31. };
  32. static u32 atmel_pinctrl_get_pinconf(const void *blob, int node)
  33. {
  34. const struct pinconf_param *params;
  35. u32 param, arg, conf = 0;
  36. u32 i;
  37. for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
  38. params = &conf_params[i];
  39. if (!fdt_get_property(blob, node, params->property, NULL))
  40. continue;
  41. param = params->param;
  42. arg = params->default_value;
  43. switch (param) {
  44. case PIN_CONFIG_BIAS_DISABLE:
  45. conf &= (~ATMEL_PIO_PUEN_MASK);
  46. conf &= (~ATMEL_PIO_PDEN_MASK);
  47. break;
  48. case PIN_CONFIG_BIAS_PULL_UP:
  49. conf |= ATMEL_PIO_PUEN_MASK;
  50. break;
  51. case PIN_CONFIG_BIAS_PULL_DOWN:
  52. conf |= ATMEL_PIO_PDEN_MASK;
  53. break;
  54. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  55. if (arg == 0)
  56. conf &= (~ATMEL_PIO_OPD_MASK);
  57. else
  58. conf |= ATMEL_PIO_OPD_MASK;
  59. break;
  60. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  61. if (arg == 0)
  62. conf |= ATMEL_PIO_SCHMITT_MASK;
  63. else
  64. conf &= (~ATMEL_PIO_SCHMITT_MASK);
  65. break;
  66. case PIN_CONFIG_INPUT_DEBOUNCE:
  67. if (arg == 0) {
  68. conf &= (~ATMEL_PIO_IFEN_MASK);
  69. conf &= (~ATMEL_PIO_IFSCEN_MASK);
  70. } else {
  71. conf |= ATMEL_PIO_IFEN_MASK;
  72. conf |= ATMEL_PIO_IFSCEN_MASK;
  73. }
  74. break;
  75. default:
  76. printf("%s: Unsupported configuration parameter: %u\n",
  77. __func__, param);
  78. break;
  79. }
  80. }
  81. return conf;
  82. }
  83. static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
  84. u32 bank)
  85. {
  86. struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
  87. struct atmel_pio4_port *bank_base =
  88. (struct atmel_pio4_port *)((u32)plat->reg_base +
  89. ATMEL_PIO_BANK_OFFSET * bank);
  90. return bank_base;
  91. }
  92. #define MAX_PINMUX_ENTRIES 40
  93. static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  94. {
  95. struct atmel_pio4_port *bank_base;
  96. const void *blob = gd->fdt_blob;
  97. int node = dev_of_offset(config);
  98. u32 offset, func, bank, line;
  99. u32 cells[MAX_PINMUX_ENTRIES];
  100. u32 i, conf;
  101. int count;
  102. conf = atmel_pinctrl_get_pinconf(blob, node);
  103. count = fdtdec_get_int_array_count(blob, node, "pinmux",
  104. cells, ARRAY_SIZE(cells));
  105. if (count < 0) {
  106. printf("%s: bad pinmux array %d\n", __func__, count);
  107. return -EINVAL;
  108. }
  109. if (count > MAX_PINMUX_ENTRIES) {
  110. printf("%s: unsupported pinmux array count %d\n",
  111. __func__, count);
  112. return -EINVAL;
  113. }
  114. for (i = 0 ; i < count; i++) {
  115. offset = ATMEL_GET_PIN_NO(cells[i]);
  116. func = ATMEL_GET_PIN_FUNC(cells[i]);
  117. bank = ATMEL_PIO_BANK(offset);
  118. line = ATMEL_PIO_LINE(offset);
  119. bank_base = atmel_pio4_bank_base(dev, bank);
  120. writel(BIT(line), &bank_base->mskr);
  121. conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
  122. conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK);
  123. writel(conf, &bank_base->cfgr);
  124. }
  125. return 0;
  126. }
  127. const struct pinctrl_ops atmel_pinctrl_ops = {
  128. .set_state = atmel_pinctrl_set_state,
  129. };
  130. static int atmel_pinctrl_probe(struct udevice *dev)
  131. {
  132. struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
  133. fdt_addr_t addr_base;
  134. dev = dev_get_parent(dev);
  135. addr_base = devfdt_get_addr(dev);
  136. if (addr_base == FDT_ADDR_T_NONE)
  137. return -EINVAL;
  138. plat->reg_base = (struct atmel_pio4_port *)addr_base;
  139. return 0;
  140. }
  141. static const struct udevice_id atmel_pinctrl_match[] = {
  142. { .compatible = "atmel,sama5d2-pinctrl" },
  143. {}
  144. };
  145. U_BOOT_DRIVER(atmel_pinctrl) = {
  146. .name = "pinctrl_atmel_pio4",
  147. .id = UCLASS_PINCTRL,
  148. .of_match = atmel_pinctrl_match,
  149. .probe = atmel_pinctrl_probe,
  150. .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
  151. .ops = &atmel_pinctrl_ops,
  152. };