smsc95xx.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright (c) 2011 The Chromium OS Authors.
  5. * Copyright (C) 2009 NVIDIA, Corporation
  6. * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <memalign.h>
  13. #include <usb.h>
  14. #include <asm/unaligned.h>
  15. #include <linux/mii.h>
  16. #include "usb_ether.h"
  17. /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
  18. /* LED defines */
  19. #define LED_GPIO_CFG (0x24)
  20. #define LED_GPIO_CFG_SPD_LED (0x01000000)
  21. #define LED_GPIO_CFG_LNK_LED (0x00100000)
  22. #define LED_GPIO_CFG_FDX_LED (0x00010000)
  23. /* Tx command words */
  24. #define TX_CMD_A_FIRST_SEG_ 0x00002000
  25. #define TX_CMD_A_LAST_SEG_ 0x00001000
  26. /* Rx status word */
  27. #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
  28. #define RX_STS_ES_ 0x00008000 /* Error Summary */
  29. /* SCSRs */
  30. #define ID_REV 0x00
  31. #define INT_STS 0x08
  32. #define TX_CFG 0x10
  33. #define TX_CFG_ON_ 0x00000004
  34. #define HW_CFG 0x14
  35. #define HW_CFG_BIR_ 0x00001000
  36. #define HW_CFG_RXDOFF_ 0x00000600
  37. #define HW_CFG_MEF_ 0x00000020
  38. #define HW_CFG_BCE_ 0x00000002
  39. #define HW_CFG_LRST_ 0x00000008
  40. #define PM_CTRL 0x20
  41. #define PM_CTL_PHY_RST_ 0x00000010
  42. #define AFC_CFG 0x2C
  43. /*
  44. * Hi watermark = 15.5Kb (~10 mtu pkts)
  45. * low watermark = 3k (~2 mtu pkts)
  46. * backpressure duration = ~ 350us
  47. * Apply FC on any frame.
  48. */
  49. #define AFC_CFG_DEFAULT 0x00F830A1
  50. #define E2P_CMD 0x30
  51. #define E2P_CMD_BUSY_ 0x80000000
  52. #define E2P_CMD_READ_ 0x00000000
  53. #define E2P_CMD_TIMEOUT_ 0x00000400
  54. #define E2P_CMD_LOADED_ 0x00000200
  55. #define E2P_CMD_ADDR_ 0x000001FF
  56. #define E2P_DATA 0x34
  57. #define BURST_CAP 0x38
  58. #define INT_EP_CTL 0x68
  59. #define INT_EP_CTL_PHY_INT_ 0x00008000
  60. #define BULK_IN_DLY 0x6C
  61. /* MAC CSRs */
  62. #define MAC_CR 0x100
  63. #define MAC_CR_MCPAS_ 0x00080000
  64. #define MAC_CR_PRMS_ 0x00040000
  65. #define MAC_CR_HPFILT_ 0x00002000
  66. #define MAC_CR_TXEN_ 0x00000008
  67. #define MAC_CR_RXEN_ 0x00000004
  68. #define ADDRH 0x104
  69. #define ADDRL 0x108
  70. #define MII_ADDR 0x114
  71. #define MII_WRITE_ 0x02
  72. #define MII_BUSY_ 0x01
  73. #define MII_READ_ 0x00 /* ~of MII Write bit */
  74. #define MII_DATA 0x118
  75. #define FLOW 0x11C
  76. #define VLAN1 0x120
  77. #define COE_CR 0x130
  78. #define Tx_COE_EN_ 0x00010000
  79. #define Rx_COE_EN_ 0x00000001
  80. /* Vendor-specific PHY Definitions */
  81. #define PHY_INT_SRC 29
  82. #define PHY_INT_MASK 30
  83. #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
  84. #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
  85. #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
  86. PHY_INT_MASK_LINK_DOWN_)
  87. /* USB Vendor Requests */
  88. #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
  89. #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
  90. /* Some extra defines */
  91. #define HS_USB_PKT_SIZE 512
  92. #define FS_USB_PKT_SIZE 64
  93. /* 5/33 is lower limit for BURST_CAP to work */
  94. #define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
  95. #define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
  96. #define DEFAULT_BULK_IN_DELAY 0x00002000
  97. #define MAX_SINGLE_PACKET_SIZE 2048
  98. #define EEPROM_MAC_OFFSET 0x01
  99. #define SMSC95XX_INTERNAL_PHY_ID 1
  100. #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
  101. /* local defines */
  102. #define SMSC95XX_BASE_NAME "sms"
  103. #define USB_CTRL_SET_TIMEOUT 5000
  104. #define USB_CTRL_GET_TIMEOUT 5000
  105. #define USB_BULK_SEND_TIMEOUT 5000
  106. #define USB_BULK_RECV_TIMEOUT 5000
  107. #define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
  108. #define PHY_CONNECT_TIMEOUT 5000
  109. #define TURBO_MODE
  110. #ifndef CONFIG_DM_ETH
  111. /* local vars */
  112. static int curr_eth_dev; /* index for name of next device detected */
  113. #endif
  114. /* driver private */
  115. struct smsc95xx_private {
  116. #ifdef CONFIG_DM_ETH
  117. struct ueth_data ueth;
  118. #endif
  119. size_t rx_urb_size; /* maximum USB URB size */
  120. u32 mac_cr; /* MAC control register value */
  121. int have_hwaddr; /* 1 if we have a hardware MAC address */
  122. };
  123. /*
  124. * Smsc95xx infrastructure commands
  125. */
  126. static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
  127. {
  128. int len;
  129. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  130. cpu_to_le32s(&data);
  131. tmpbuf[0] = data;
  132. len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
  133. USB_VENDOR_REQUEST_WRITE_REGISTER,
  134. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  135. 0, index, tmpbuf, sizeof(data),
  136. USB_CTRL_SET_TIMEOUT);
  137. if (len != sizeof(data)) {
  138. debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
  139. index, data, len);
  140. return -EIO;
  141. }
  142. return 0;
  143. }
  144. static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
  145. {
  146. int len;
  147. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  148. len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
  149. USB_VENDOR_REQUEST_READ_REGISTER,
  150. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  151. 0, index, tmpbuf, sizeof(*data),
  152. USB_CTRL_GET_TIMEOUT);
  153. *data = tmpbuf[0];
  154. if (len != sizeof(*data)) {
  155. debug("smsc95xx_read_reg failed: index=%d, len=%d",
  156. index, len);
  157. return -EIO;
  158. }
  159. le32_to_cpus(data);
  160. return 0;
  161. }
  162. /* Loop until the read is completed with timeout */
  163. static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
  164. {
  165. unsigned long start_time = get_timer(0);
  166. u32 val;
  167. do {
  168. smsc95xx_read_reg(udev, MII_ADDR, &val);
  169. if (!(val & MII_BUSY_))
  170. return 0;
  171. } while (get_timer(start_time) < 1000);
  172. return -ETIMEDOUT;
  173. }
  174. static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
  175. {
  176. u32 val, addr;
  177. /* confirm MII not busy */
  178. if (smsc95xx_phy_wait_not_busy(udev)) {
  179. debug("MII is busy in smsc95xx_mdio_read\n");
  180. return -ETIMEDOUT;
  181. }
  182. /* set the address, index & direction (read from PHY) */
  183. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  184. smsc95xx_write_reg(udev, MII_ADDR, addr);
  185. if (smsc95xx_phy_wait_not_busy(udev)) {
  186. debug("Timed out reading MII reg %02X\n", idx);
  187. return -ETIMEDOUT;
  188. }
  189. smsc95xx_read_reg(udev, MII_DATA, &val);
  190. return (u16)(val & 0xFFFF);
  191. }
  192. static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
  193. int regval)
  194. {
  195. u32 val, addr;
  196. /* confirm MII not busy */
  197. if (smsc95xx_phy_wait_not_busy(udev)) {
  198. debug("MII is busy in smsc95xx_mdio_write\n");
  199. return;
  200. }
  201. val = regval;
  202. smsc95xx_write_reg(udev, MII_DATA, val);
  203. /* set the address, index & direction (write to PHY) */
  204. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  205. smsc95xx_write_reg(udev, MII_ADDR, addr);
  206. if (smsc95xx_phy_wait_not_busy(udev))
  207. debug("Timed out writing MII reg %02X\n", idx);
  208. }
  209. static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
  210. {
  211. unsigned long start_time = get_timer(0);
  212. u32 val;
  213. do {
  214. smsc95xx_read_reg(udev, E2P_CMD, &val);
  215. if (!(val & E2P_CMD_BUSY_))
  216. return 0;
  217. udelay(40);
  218. } while (get_timer(start_time) < 1 * 1000 * 1000);
  219. debug("EEPROM is busy\n");
  220. return -ETIMEDOUT;
  221. }
  222. static int smsc95xx_wait_eeprom(struct usb_device *udev)
  223. {
  224. unsigned long start_time = get_timer(0);
  225. u32 val;
  226. do {
  227. smsc95xx_read_reg(udev, E2P_CMD, &val);
  228. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  229. break;
  230. udelay(40);
  231. } while (get_timer(start_time) < 1 * 1000 * 1000);
  232. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  233. debug("EEPROM read operation timeout\n");
  234. return -ETIMEDOUT;
  235. }
  236. return 0;
  237. }
  238. static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
  239. u8 *data)
  240. {
  241. u32 val;
  242. int i, ret;
  243. ret = smsc95xx_eeprom_confirm_not_busy(udev);
  244. if (ret)
  245. return ret;
  246. for (i = 0; i < length; i++) {
  247. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  248. smsc95xx_write_reg(udev, E2P_CMD, val);
  249. ret = smsc95xx_wait_eeprom(udev);
  250. if (ret < 0)
  251. return ret;
  252. smsc95xx_read_reg(udev, E2P_DATA, &val);
  253. data[i] = val & 0xFF;
  254. offset++;
  255. }
  256. return 0;
  257. }
  258. /*
  259. * mii_nway_restart - restart NWay (autonegotiation) for this interface
  260. *
  261. * Returns 0 on success, negative on error.
  262. */
  263. static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
  264. {
  265. int bmcr;
  266. int r = -1;
  267. /* if autoneg is off, it's an error */
  268. bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
  269. if (bmcr & BMCR_ANENABLE) {
  270. bmcr |= BMCR_ANRESTART;
  271. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
  272. r = 0;
  273. }
  274. return r;
  275. }
  276. static int smsc95xx_phy_initialize(struct usb_device *udev,
  277. struct ueth_data *dev)
  278. {
  279. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
  280. smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
  281. ADVERTISE_ALL | ADVERTISE_CSMA |
  282. ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  283. /* read to clear */
  284. smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
  285. smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
  286. PHY_INT_MASK_DEFAULT_);
  287. mii_nway_restart(udev, dev);
  288. debug("phy initialised succesfully\n");
  289. return 0;
  290. }
  291. static int smsc95xx_init_mac_address(unsigned char *enetaddr,
  292. struct usb_device *udev)
  293. {
  294. int ret;
  295. /* try reading mac address from EEPROM */
  296. ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
  297. if (ret)
  298. return ret;
  299. if (is_valid_ethaddr(enetaddr)) {
  300. /* eeprom values are valid so use them */
  301. debug("MAC address read from EEPROM\n");
  302. return 0;
  303. }
  304. /*
  305. * No eeprom, or eeprom values are invalid. Generating a random MAC
  306. * address is not safe. Just return an error.
  307. */
  308. debug("Invalid MAC address read from EEPROM\n");
  309. return -ENXIO;
  310. }
  311. static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
  312. struct smsc95xx_private *priv,
  313. unsigned char *enetaddr)
  314. {
  315. u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
  316. u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
  317. int ret;
  318. /* set hardware address */
  319. debug("** %s()\n", __func__);
  320. ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
  321. if (ret < 0)
  322. return ret;
  323. ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
  324. if (ret < 0)
  325. return ret;
  326. debug("MAC %pM\n", enetaddr);
  327. priv->have_hwaddr = 1;
  328. return 0;
  329. }
  330. /* Enable or disable Tx & Rx checksum offload engines */
  331. static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
  332. int use_rx_csum)
  333. {
  334. u32 read_buf;
  335. int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
  336. if (ret < 0)
  337. return ret;
  338. if (use_tx_csum)
  339. read_buf |= Tx_COE_EN_;
  340. else
  341. read_buf &= ~Tx_COE_EN_;
  342. if (use_rx_csum)
  343. read_buf |= Rx_COE_EN_;
  344. else
  345. read_buf &= ~Rx_COE_EN_;
  346. ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
  347. if (ret < 0)
  348. return ret;
  349. debug("COE_CR = 0x%08x\n", read_buf);
  350. return 0;
  351. }
  352. static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
  353. {
  354. /* No multicast in u-boot */
  355. priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  356. }
  357. /* starts the TX path */
  358. static void smsc95xx_start_tx_path(struct usb_device *udev,
  359. struct smsc95xx_private *priv)
  360. {
  361. u32 reg_val;
  362. /* Enable Tx at MAC */
  363. priv->mac_cr |= MAC_CR_TXEN_;
  364. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  365. /* Enable Tx at SCSRs */
  366. reg_val = TX_CFG_ON_;
  367. smsc95xx_write_reg(udev, TX_CFG, reg_val);
  368. }
  369. /* Starts the Receive path */
  370. static void smsc95xx_start_rx_path(struct usb_device *udev,
  371. struct smsc95xx_private *priv)
  372. {
  373. priv->mac_cr |= MAC_CR_RXEN_;
  374. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  375. }
  376. static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
  377. struct smsc95xx_private *priv,
  378. unsigned char *enetaddr)
  379. {
  380. int ret;
  381. u32 write_buf;
  382. u32 read_buf;
  383. u32 burst_cap;
  384. int timeout;
  385. #define TIMEOUT_RESOLUTION 50 /* ms */
  386. int link_detected;
  387. debug("** %s()\n", __func__);
  388. dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
  389. write_buf = HW_CFG_LRST_;
  390. ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
  391. if (ret < 0)
  392. return ret;
  393. timeout = 0;
  394. do {
  395. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  396. if (ret < 0)
  397. return ret;
  398. udelay(10 * 1000);
  399. timeout++;
  400. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  401. if (timeout >= 100) {
  402. debug("timeout waiting for completion of Lite Reset\n");
  403. return -ETIMEDOUT;
  404. }
  405. write_buf = PM_CTL_PHY_RST_;
  406. ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
  407. if (ret < 0)
  408. return ret;
  409. timeout = 0;
  410. do {
  411. ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
  412. if (ret < 0)
  413. return ret;
  414. udelay(10 * 1000);
  415. timeout++;
  416. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  417. if (timeout >= 100) {
  418. debug("timeout waiting for PHY Reset\n");
  419. return -ETIMEDOUT;
  420. }
  421. #ifndef CONFIG_DM_ETH
  422. if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
  423. 0)
  424. priv->have_hwaddr = 1;
  425. #endif
  426. if (!priv->have_hwaddr) {
  427. puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
  428. return -EADDRNOTAVAIL;
  429. }
  430. ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
  431. if (ret < 0)
  432. return ret;
  433. #ifdef TURBO_MODE
  434. if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
  435. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  436. priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  437. } else {
  438. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  439. priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  440. }
  441. #else
  442. burst_cap = 0;
  443. priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  444. #endif
  445. debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
  446. ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
  447. if (ret < 0)
  448. return ret;
  449. ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
  450. if (ret < 0)
  451. return ret;
  452. debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
  453. read_buf = DEFAULT_BULK_IN_DELAY;
  454. ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
  455. if (ret < 0)
  456. return ret;
  457. ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
  458. if (ret < 0)
  459. return ret;
  460. debug("Read Value from BULK_IN_DLY after writing: "
  461. "0x%08x\n", read_buf);
  462. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  463. if (ret < 0)
  464. return ret;
  465. debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
  466. #ifdef TURBO_MODE
  467. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  468. #endif
  469. read_buf &= ~HW_CFG_RXDOFF_;
  470. #define NET_IP_ALIGN 0
  471. read_buf |= NET_IP_ALIGN << 9;
  472. ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
  473. if (ret < 0)
  474. return ret;
  475. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  476. if (ret < 0)
  477. return ret;
  478. debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  479. write_buf = 0xFFFFFFFF;
  480. ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
  481. if (ret < 0)
  482. return ret;
  483. ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
  484. if (ret < 0)
  485. return ret;
  486. debug("ID_REV = 0x%08x\n", read_buf);
  487. /* Configure GPIO pins as LED outputs */
  488. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  489. LED_GPIO_CFG_FDX_LED;
  490. ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
  491. if (ret < 0)
  492. return ret;
  493. debug("LED_GPIO_CFG set\n");
  494. /* Init Tx */
  495. write_buf = 0;
  496. ret = smsc95xx_write_reg(udev, FLOW, write_buf);
  497. if (ret < 0)
  498. return ret;
  499. read_buf = AFC_CFG_DEFAULT;
  500. ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
  501. if (ret < 0)
  502. return ret;
  503. ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
  504. if (ret < 0)
  505. return ret;
  506. /* Init Rx. Set Vlan */
  507. write_buf = (u32)ETH_P_8021Q;
  508. ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
  509. if (ret < 0)
  510. return ret;
  511. /* Disable checksum offload engines */
  512. ret = smsc95xx_set_csums(udev, 0, 0);
  513. if (ret < 0) {
  514. debug("Failed to set csum offload: %d\n", ret);
  515. return ret;
  516. }
  517. smsc95xx_set_multicast(priv);
  518. ret = smsc95xx_phy_initialize(udev, dev);
  519. if (ret < 0)
  520. return ret;
  521. ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
  522. if (ret < 0)
  523. return ret;
  524. /* enable PHY interrupts */
  525. read_buf |= INT_EP_CTL_PHY_INT_;
  526. ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
  527. if (ret < 0)
  528. return ret;
  529. smsc95xx_start_tx_path(udev, priv);
  530. smsc95xx_start_rx_path(udev, priv);
  531. timeout = 0;
  532. do {
  533. link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
  534. & BMSR_LSTATUS;
  535. if (!link_detected) {
  536. if (timeout == 0)
  537. printf("Waiting for Ethernet connection... ");
  538. udelay(TIMEOUT_RESOLUTION * 1000);
  539. timeout += TIMEOUT_RESOLUTION;
  540. }
  541. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  542. if (link_detected) {
  543. if (timeout != 0)
  544. printf("done.\n");
  545. } else {
  546. printf("unable to connect.\n");
  547. return -EIO;
  548. }
  549. return 0;
  550. }
  551. static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
  552. {
  553. int err;
  554. int actual_len;
  555. u32 tx_cmd_a;
  556. u32 tx_cmd_b;
  557. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  558. PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
  559. debug("** %s(), len %d, buf %#x\n", __func__, length,
  560. (unsigned int)(ulong)msg);
  561. if (length > PKTSIZE)
  562. return -ENOSPC;
  563. tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  564. tx_cmd_b = (u32)length;
  565. cpu_to_le32s(&tx_cmd_a);
  566. cpu_to_le32s(&tx_cmd_b);
  567. /* prepend cmd_a and cmd_b */
  568. memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
  569. memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
  570. memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
  571. length);
  572. err = usb_bulk_msg(dev->pusb_dev,
  573. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  574. (void *)msg,
  575. length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
  576. &actual_len,
  577. USB_BULK_SEND_TIMEOUT);
  578. debug("Tx: len = %u, actual = %u, err = %d\n",
  579. (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
  580. (unsigned int)actual_len, err);
  581. return err;
  582. }
  583. #ifndef CONFIG_DM_ETH
  584. /*
  585. * Smsc95xx callbacks
  586. */
  587. static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
  588. {
  589. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  590. struct usb_device *udev = dev->pusb_dev;
  591. struct smsc95xx_private *priv =
  592. (struct smsc95xx_private *)dev->dev_priv;
  593. return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
  594. }
  595. static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
  596. {
  597. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  598. return smsc95xx_send_common(dev, packet, length);
  599. }
  600. static int smsc95xx_recv(struct eth_device *eth)
  601. {
  602. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  603. DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
  604. unsigned char *buf_ptr;
  605. int err;
  606. int actual_len;
  607. u32 packet_len;
  608. int cur_buf_align;
  609. debug("** %s()\n", __func__);
  610. err = usb_bulk_msg(dev->pusb_dev,
  611. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  612. (void *)recv_buf, RX_URB_SIZE, &actual_len,
  613. USB_BULK_RECV_TIMEOUT);
  614. debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
  615. actual_len, err);
  616. if (err != 0) {
  617. debug("Rx: failed to receive\n");
  618. return -err;
  619. }
  620. if (actual_len > RX_URB_SIZE) {
  621. debug("Rx: received too many bytes %d\n", actual_len);
  622. return -ENOSPC;
  623. }
  624. buf_ptr = recv_buf;
  625. while (actual_len > 0) {
  626. /*
  627. * 1st 4 bytes contain the length of the actual data plus error
  628. * info. Extract data length.
  629. */
  630. if (actual_len < sizeof(packet_len)) {
  631. debug("Rx: incomplete packet length\n");
  632. return -EIO;
  633. }
  634. memcpy(&packet_len, buf_ptr, sizeof(packet_len));
  635. le32_to_cpus(&packet_len);
  636. if (packet_len & RX_STS_ES_) {
  637. debug("Rx: Error header=%#x", packet_len);
  638. return -EIO;
  639. }
  640. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  641. if (packet_len > actual_len - sizeof(packet_len)) {
  642. debug("Rx: too large packet: %d\n", packet_len);
  643. return -EIO;
  644. }
  645. /* Notify net stack */
  646. net_process_received_packet(buf_ptr + sizeof(packet_len),
  647. packet_len - 4);
  648. /* Adjust for next iteration */
  649. actual_len -= sizeof(packet_len) + packet_len;
  650. buf_ptr += sizeof(packet_len) + packet_len;
  651. cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
  652. if (cur_buf_align & 0x03) {
  653. int align = 4 - (cur_buf_align & 0x03);
  654. actual_len -= align;
  655. buf_ptr += align;
  656. }
  657. }
  658. return err;
  659. }
  660. static void smsc95xx_halt(struct eth_device *eth)
  661. {
  662. debug("** %s()\n", __func__);
  663. }
  664. static int smsc95xx_write_hwaddr(struct eth_device *eth)
  665. {
  666. struct ueth_data *dev = eth->priv;
  667. struct usb_device *udev = dev->pusb_dev;
  668. struct smsc95xx_private *priv = dev->dev_priv;
  669. return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
  670. }
  671. /*
  672. * SMSC probing functions
  673. */
  674. void smsc95xx_eth_before_probe(void)
  675. {
  676. curr_eth_dev = 0;
  677. }
  678. struct smsc95xx_dongle {
  679. unsigned short vendor;
  680. unsigned short product;
  681. };
  682. static const struct smsc95xx_dongle smsc95xx_dongles[] = {
  683. { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
  684. { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
  685. { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
  686. { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
  687. { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
  688. { 0x0000, 0x0000 } /* END - Do not remove */
  689. };
  690. /* Probe to see if a new device is actually an SMSC device */
  691. int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
  692. struct ueth_data *ss)
  693. {
  694. struct usb_interface *iface;
  695. struct usb_interface_descriptor *iface_desc;
  696. int i;
  697. /* let's examine the device now */
  698. iface = &dev->config.if_desc[ifnum];
  699. iface_desc = &dev->config.if_desc[ifnum].desc;
  700. for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
  701. if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
  702. dev->descriptor.idProduct == smsc95xx_dongles[i].product)
  703. /* Found a supported dongle */
  704. break;
  705. }
  706. if (smsc95xx_dongles[i].vendor == 0)
  707. return 0;
  708. /* At this point, we know we've got a live one */
  709. debug("\n\nUSB Ethernet device detected\n");
  710. memset(ss, '\0', sizeof(struct ueth_data));
  711. /* Initialize the ueth_data structure with some useful info */
  712. ss->ifnum = ifnum;
  713. ss->pusb_dev = dev;
  714. ss->subclass = iface_desc->bInterfaceSubClass;
  715. ss->protocol = iface_desc->bInterfaceProtocol;
  716. /*
  717. * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
  718. * We will ignore any others.
  719. */
  720. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  721. /* is it an BULK endpoint? */
  722. if ((iface->ep_desc[i].bmAttributes &
  723. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  724. if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
  725. ss->ep_in =
  726. iface->ep_desc[i].bEndpointAddress &
  727. USB_ENDPOINT_NUMBER_MASK;
  728. else
  729. ss->ep_out =
  730. iface->ep_desc[i].bEndpointAddress &
  731. USB_ENDPOINT_NUMBER_MASK;
  732. }
  733. /* is it an interrupt endpoint? */
  734. if ((iface->ep_desc[i].bmAttributes &
  735. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  736. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  737. USB_ENDPOINT_NUMBER_MASK;
  738. ss->irqinterval = iface->ep_desc[i].bInterval;
  739. }
  740. }
  741. debug("Endpoints In %d Out %d Int %d\n",
  742. ss->ep_in, ss->ep_out, ss->ep_int);
  743. /* Do some basic sanity checks, and bail if we find a problem */
  744. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  745. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  746. debug("Problems with device\n");
  747. return 0;
  748. }
  749. dev->privptr = (void *)ss;
  750. /* alloc driver private */
  751. ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
  752. if (!ss->dev_priv)
  753. return 0;
  754. return 1;
  755. }
  756. int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  757. struct eth_device *eth)
  758. {
  759. debug("** %s()\n", __func__);
  760. if (!eth) {
  761. debug("%s: missing parameter.\n", __func__);
  762. return 0;
  763. }
  764. sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
  765. eth->init = smsc95xx_init;
  766. eth->send = smsc95xx_send;
  767. eth->recv = smsc95xx_recv;
  768. eth->halt = smsc95xx_halt;
  769. eth->write_hwaddr = smsc95xx_write_hwaddr;
  770. eth->priv = ss;
  771. return 1;
  772. }
  773. #endif /* !CONFIG_DM_ETH */
  774. #ifdef CONFIG_DM_ETH
  775. static int smsc95xx_eth_start(struct udevice *dev)
  776. {
  777. struct usb_device *udev = dev_get_parent_priv(dev);
  778. struct smsc95xx_private *priv = dev_get_priv(dev);
  779. struct eth_pdata *pdata = dev_get_platdata(dev);
  780. /* Driver-model Ethernet ensures we have this */
  781. priv->have_hwaddr = 1;
  782. return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
  783. }
  784. void smsc95xx_eth_stop(struct udevice *dev)
  785. {
  786. debug("** %s()\n", __func__);
  787. }
  788. int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
  789. {
  790. struct smsc95xx_private *priv = dev_get_priv(dev);
  791. return smsc95xx_send_common(&priv->ueth, packet, length);
  792. }
  793. int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  794. {
  795. struct smsc95xx_private *priv = dev_get_priv(dev);
  796. struct ueth_data *ueth = &priv->ueth;
  797. uint8_t *ptr;
  798. int ret, len;
  799. u32 packet_len;
  800. len = usb_ether_get_rx_bytes(ueth, &ptr);
  801. debug("%s: first try, len=%d\n", __func__, len);
  802. if (!len) {
  803. if (!(flags & ETH_RECV_CHECK_DEVICE))
  804. return -EAGAIN;
  805. ret = usb_ether_receive(ueth, RX_URB_SIZE);
  806. if (ret == -EAGAIN)
  807. return ret;
  808. len = usb_ether_get_rx_bytes(ueth, &ptr);
  809. debug("%s: second try, len=%d\n", __func__, len);
  810. }
  811. /*
  812. * 1st 4 bytes contain the length of the actual data plus error info.
  813. * Extract data length.
  814. */
  815. if (len < sizeof(packet_len)) {
  816. debug("Rx: incomplete packet length\n");
  817. goto err;
  818. }
  819. memcpy(&packet_len, ptr, sizeof(packet_len));
  820. le32_to_cpus(&packet_len);
  821. if (packet_len & RX_STS_ES_) {
  822. debug("Rx: Error header=%#x", packet_len);
  823. goto err;
  824. }
  825. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  826. if (packet_len > len - sizeof(packet_len)) {
  827. debug("Rx: too large packet: %d\n", packet_len);
  828. goto err;
  829. }
  830. *packetp = ptr + sizeof(packet_len);
  831. return packet_len - 4;
  832. err:
  833. usb_ether_advance_rxbuf(ueth, -1);
  834. return -EINVAL;
  835. }
  836. static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  837. {
  838. struct smsc95xx_private *priv = dev_get_priv(dev);
  839. packet_len = ALIGN(packet_len + sizeof(u32), 4);
  840. usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
  841. return 0;
  842. }
  843. int smsc95xx_write_hwaddr(struct udevice *dev)
  844. {
  845. struct usb_device *udev = dev_get_parent_priv(dev);
  846. struct eth_pdata *pdata = dev_get_platdata(dev);
  847. struct smsc95xx_private *priv = dev_get_priv(dev);
  848. return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
  849. }
  850. int smsc95xx_read_rom_hwaddr(struct udevice *dev)
  851. {
  852. struct usb_device *udev = dev_get_parent_priv(dev);
  853. struct eth_pdata *pdata = dev_get_platdata(dev);
  854. int ret;
  855. ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
  856. if (ret)
  857. memset(pdata->enetaddr, 0, 6);
  858. return 0;
  859. }
  860. static int smsc95xx_eth_probe(struct udevice *dev)
  861. {
  862. struct smsc95xx_private *priv = dev_get_priv(dev);
  863. struct ueth_data *ueth = &priv->ueth;
  864. return usb_ether_register(dev, ueth, RX_URB_SIZE);
  865. }
  866. static const struct eth_ops smsc95xx_eth_ops = {
  867. .start = smsc95xx_eth_start,
  868. .send = smsc95xx_eth_send,
  869. .recv = smsc95xx_eth_recv,
  870. .free_pkt = smsc95xx_free_pkt,
  871. .stop = smsc95xx_eth_stop,
  872. .write_hwaddr = smsc95xx_write_hwaddr,
  873. .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
  874. };
  875. U_BOOT_DRIVER(smsc95xx_eth) = {
  876. .name = "smsc95xx_eth",
  877. .id = UCLASS_ETH,
  878. .probe = smsc95xx_eth_probe,
  879. .ops = &smsc95xx_eth_ops,
  880. .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
  881. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  882. };
  883. static const struct usb_device_id smsc95xx_eth_id_table[] = {
  884. { USB_DEVICE(0x05ac, 0x1402) },
  885. { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
  886. { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
  887. { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
  888. { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
  889. { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
  890. { } /* Terminating entry */
  891. };
  892. U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
  893. #endif