hns3_enet.c 93 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (c) 2016-2017 Hisilicon Limited.
  3. #include <linux/dma-mapping.h>
  4. #include <linux/etherdevice.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/if_vlan.h>
  7. #include <linux/ip.h>
  8. #include <linux/ipv6.h>
  9. #include <linux/module.h>
  10. #include <linux/pci.h>
  11. #include <linux/skbuff.h>
  12. #include <linux/sctp.h>
  13. #include <linux/vermagic.h>
  14. #include <net/gre.h>
  15. #include <net/pkt_cls.h>
  16. #include <net/vxlan.h>
  17. #include "hnae3.h"
  18. #include "hns3_enet.h"
  19. static void hns3_clear_all_ring(struct hnae3_handle *h);
  20. static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
  21. static const char hns3_driver_name[] = "hns3";
  22. const char hns3_driver_version[] = VERMAGIC_STRING;
  23. static const char hns3_driver_string[] =
  24. "Hisilicon Ethernet Network Driver for Hip08 Family";
  25. static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
  26. static struct hnae3_client client;
  27. /* hns3_pci_tbl - PCI Device ID Table
  28. *
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static const struct pci_device_id hns3_pci_tbl[] = {
  35. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  36. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  37. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
  38. HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  39. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
  40. HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  41. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
  42. HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  43. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
  44. HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  45. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
  46. HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  47. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
  48. {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
  49. HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  50. /* required last entry */
  51. {0, }
  52. };
  53. MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
  54. static irqreturn_t hns3_irq_handle(int irq, void *vector)
  55. {
  56. struct hns3_enet_tqp_vector *tqp_vector = vector;
  57. napi_schedule(&tqp_vector->napi);
  58. return IRQ_HANDLED;
  59. }
  60. static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
  61. {
  62. struct hns3_enet_tqp_vector *tqp_vectors;
  63. unsigned int i;
  64. for (i = 0; i < priv->vector_num; i++) {
  65. tqp_vectors = &priv->tqp_vector[i];
  66. if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
  67. continue;
  68. /* release the irq resource */
  69. free_irq(tqp_vectors->vector_irq, tqp_vectors);
  70. tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
  71. }
  72. }
  73. static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
  74. {
  75. struct hns3_enet_tqp_vector *tqp_vectors;
  76. int txrx_int_idx = 0;
  77. int rx_int_idx = 0;
  78. int tx_int_idx = 0;
  79. unsigned int i;
  80. int ret;
  81. for (i = 0; i < priv->vector_num; i++) {
  82. tqp_vectors = &priv->tqp_vector[i];
  83. if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
  84. continue;
  85. if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
  86. snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
  87. "%s-%s-%d", priv->netdev->name, "TxRx",
  88. txrx_int_idx++);
  89. txrx_int_idx++;
  90. } else if (tqp_vectors->rx_group.ring) {
  91. snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
  92. "%s-%s-%d", priv->netdev->name, "Rx",
  93. rx_int_idx++);
  94. } else if (tqp_vectors->tx_group.ring) {
  95. snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
  96. "%s-%s-%d", priv->netdev->name, "Tx",
  97. tx_int_idx++);
  98. } else {
  99. /* Skip this unused q_vector */
  100. continue;
  101. }
  102. tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
  103. ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
  104. tqp_vectors->name,
  105. tqp_vectors);
  106. if (ret) {
  107. netdev_err(priv->netdev, "request irq(%d) fail\n",
  108. tqp_vectors->vector_irq);
  109. return ret;
  110. }
  111. tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
  112. }
  113. return 0;
  114. }
  115. static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
  116. u32 mask_en)
  117. {
  118. writel(mask_en, tqp_vector->mask_addr);
  119. }
  120. static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
  121. {
  122. napi_enable(&tqp_vector->napi);
  123. /* enable vector */
  124. hns3_mask_vector_irq(tqp_vector, 1);
  125. }
  126. static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
  127. {
  128. /* disable vector */
  129. hns3_mask_vector_irq(tqp_vector, 0);
  130. disable_irq(tqp_vector->vector_irq);
  131. napi_disable(&tqp_vector->napi);
  132. }
  133. void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
  134. u32 rl_value)
  135. {
  136. u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
  137. /* this defines the configuration for RL (Interrupt Rate Limiter).
  138. * Rl defines rate of interrupts i.e. number of interrupts-per-second
  139. * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
  140. */
  141. if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
  142. !tqp_vector->rx_group.coal.gl_adapt_enable)
  143. /* According to the hardware, the range of rl_reg is
  144. * 0-59 and the unit is 4.
  145. */
  146. rl_reg |= HNS3_INT_RL_ENABLE_MASK;
  147. writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
  148. }
  149. void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
  150. u32 gl_value)
  151. {
  152. u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
  153. writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
  154. }
  155. void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
  156. u32 gl_value)
  157. {
  158. u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
  159. writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
  160. }
  161. static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
  162. struct hns3_nic_priv *priv)
  163. {
  164. /* initialize the configuration for interrupt coalescing.
  165. * 1. GL (Interrupt Gap Limiter)
  166. * 2. RL (Interrupt Rate Limiter)
  167. */
  168. /* Default: enable interrupt coalescing self-adaptive and GL */
  169. tqp_vector->tx_group.coal.gl_adapt_enable = 1;
  170. tqp_vector->rx_group.coal.gl_adapt_enable = 1;
  171. tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
  172. tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
  173. tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
  174. tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
  175. tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
  176. }
  177. static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
  178. struct hns3_nic_priv *priv)
  179. {
  180. struct hnae3_handle *h = priv->ae_handle;
  181. hns3_set_vector_coalesce_tx_gl(tqp_vector,
  182. tqp_vector->tx_group.coal.int_gl);
  183. hns3_set_vector_coalesce_rx_gl(tqp_vector,
  184. tqp_vector->rx_group.coal.int_gl);
  185. hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
  186. }
  187. static int hns3_nic_set_real_num_queue(struct net_device *netdev)
  188. {
  189. struct hnae3_handle *h = hns3_get_handle(netdev);
  190. struct hnae3_knic_private_info *kinfo = &h->kinfo;
  191. unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
  192. int i, ret;
  193. if (kinfo->num_tc <= 1) {
  194. netdev_reset_tc(netdev);
  195. } else {
  196. ret = netdev_set_num_tc(netdev, kinfo->num_tc);
  197. if (ret) {
  198. netdev_err(netdev,
  199. "netdev_set_num_tc fail, ret=%d!\n", ret);
  200. return ret;
  201. }
  202. for (i = 0; i < HNAE3_MAX_TC; i++) {
  203. if (!kinfo->tc_info[i].enable)
  204. continue;
  205. netdev_set_tc_queue(netdev,
  206. kinfo->tc_info[i].tc,
  207. kinfo->tc_info[i].tqp_count,
  208. kinfo->tc_info[i].tqp_offset);
  209. }
  210. }
  211. ret = netif_set_real_num_tx_queues(netdev, queue_size);
  212. if (ret) {
  213. netdev_err(netdev,
  214. "netif_set_real_num_tx_queues fail, ret=%d!\n",
  215. ret);
  216. return ret;
  217. }
  218. ret = netif_set_real_num_rx_queues(netdev, queue_size);
  219. if (ret) {
  220. netdev_err(netdev,
  221. "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
  222. return ret;
  223. }
  224. return 0;
  225. }
  226. static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
  227. {
  228. u16 free_tqps, max_rss_size, max_tqps;
  229. h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
  230. max_tqps = h->kinfo.num_tc * max_rss_size;
  231. return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
  232. }
  233. static int hns3_nic_net_up(struct net_device *netdev)
  234. {
  235. struct hns3_nic_priv *priv = netdev_priv(netdev);
  236. struct hnae3_handle *h = priv->ae_handle;
  237. int i, j;
  238. int ret;
  239. ret = hns3_nic_reset_all_ring(h);
  240. if (ret)
  241. return ret;
  242. /* get irq resource for all vectors */
  243. ret = hns3_nic_init_irq(priv);
  244. if (ret) {
  245. netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
  246. return ret;
  247. }
  248. /* enable the vectors */
  249. for (i = 0; i < priv->vector_num; i++)
  250. hns3_vector_enable(&priv->tqp_vector[i]);
  251. /* start the ae_dev */
  252. ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
  253. if (ret)
  254. goto out_start_err;
  255. clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
  256. return 0;
  257. out_start_err:
  258. for (j = i - 1; j >= 0; j--)
  259. hns3_vector_disable(&priv->tqp_vector[j]);
  260. hns3_nic_uninit_irq(priv);
  261. return ret;
  262. }
  263. static int hns3_nic_net_open(struct net_device *netdev)
  264. {
  265. struct hns3_nic_priv *priv = netdev_priv(netdev);
  266. struct hnae3_handle *h = hns3_get_handle(netdev);
  267. struct hnae3_knic_private_info *kinfo;
  268. int i, ret;
  269. netif_carrier_off(netdev);
  270. ret = hns3_nic_set_real_num_queue(netdev);
  271. if (ret)
  272. return ret;
  273. ret = hns3_nic_net_up(netdev);
  274. if (ret) {
  275. netdev_err(netdev,
  276. "hns net up fail, ret=%d!\n", ret);
  277. return ret;
  278. }
  279. kinfo = &h->kinfo;
  280. for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
  281. netdev_set_prio_tc_map(netdev, i,
  282. kinfo->prio_tc[i]);
  283. }
  284. priv->ae_handle->last_reset_time = jiffies;
  285. return 0;
  286. }
  287. static void hns3_nic_net_down(struct net_device *netdev)
  288. {
  289. struct hns3_nic_priv *priv = netdev_priv(netdev);
  290. const struct hnae3_ae_ops *ops;
  291. int i;
  292. if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
  293. return;
  294. /* disable vectors */
  295. for (i = 0; i < priv->vector_num; i++)
  296. hns3_vector_disable(&priv->tqp_vector[i]);
  297. /* stop ae_dev */
  298. ops = priv->ae_handle->ae_algo->ops;
  299. if (ops->stop)
  300. ops->stop(priv->ae_handle);
  301. /* free irq resources */
  302. hns3_nic_uninit_irq(priv);
  303. hns3_clear_all_ring(priv->ae_handle);
  304. }
  305. static int hns3_nic_net_stop(struct net_device *netdev)
  306. {
  307. netif_tx_stop_all_queues(netdev);
  308. netif_carrier_off(netdev);
  309. hns3_nic_net_down(netdev);
  310. return 0;
  311. }
  312. static int hns3_nic_uc_sync(struct net_device *netdev,
  313. const unsigned char *addr)
  314. {
  315. struct hnae3_handle *h = hns3_get_handle(netdev);
  316. if (h->ae_algo->ops->add_uc_addr)
  317. return h->ae_algo->ops->add_uc_addr(h, addr);
  318. return 0;
  319. }
  320. static int hns3_nic_uc_unsync(struct net_device *netdev,
  321. const unsigned char *addr)
  322. {
  323. struct hnae3_handle *h = hns3_get_handle(netdev);
  324. if (h->ae_algo->ops->rm_uc_addr)
  325. return h->ae_algo->ops->rm_uc_addr(h, addr);
  326. return 0;
  327. }
  328. static int hns3_nic_mc_sync(struct net_device *netdev,
  329. const unsigned char *addr)
  330. {
  331. struct hnae3_handle *h = hns3_get_handle(netdev);
  332. if (h->ae_algo->ops->add_mc_addr)
  333. return h->ae_algo->ops->add_mc_addr(h, addr);
  334. return 0;
  335. }
  336. static int hns3_nic_mc_unsync(struct net_device *netdev,
  337. const unsigned char *addr)
  338. {
  339. struct hnae3_handle *h = hns3_get_handle(netdev);
  340. if (h->ae_algo->ops->rm_mc_addr)
  341. return h->ae_algo->ops->rm_mc_addr(h, addr);
  342. return 0;
  343. }
  344. static void hns3_nic_set_rx_mode(struct net_device *netdev)
  345. {
  346. struct hnae3_handle *h = hns3_get_handle(netdev);
  347. if (h->ae_algo->ops->set_promisc_mode) {
  348. if (netdev->flags & IFF_PROMISC)
  349. h->ae_algo->ops->set_promisc_mode(h, true, true);
  350. else if (netdev->flags & IFF_ALLMULTI)
  351. h->ae_algo->ops->set_promisc_mode(h, false, true);
  352. else
  353. h->ae_algo->ops->set_promisc_mode(h, false, false);
  354. }
  355. if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
  356. netdev_err(netdev, "sync uc address fail\n");
  357. if (netdev->flags & IFF_MULTICAST) {
  358. if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
  359. netdev_err(netdev, "sync mc address fail\n");
  360. if (h->ae_algo->ops->update_mta_status)
  361. h->ae_algo->ops->update_mta_status(h);
  362. }
  363. }
  364. static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
  365. u16 *mss, u32 *type_cs_vlan_tso)
  366. {
  367. u32 l4_offset, hdr_len;
  368. union l3_hdr_info l3;
  369. union l4_hdr_info l4;
  370. u32 l4_paylen;
  371. int ret;
  372. if (!skb_is_gso(skb))
  373. return 0;
  374. ret = skb_cow_head(skb, 0);
  375. if (ret)
  376. return ret;
  377. l3.hdr = skb_network_header(skb);
  378. l4.hdr = skb_transport_header(skb);
  379. /* Software should clear the IPv4's checksum field when tso is
  380. * needed.
  381. */
  382. if (l3.v4->version == 4)
  383. l3.v4->check = 0;
  384. /* tunnel packet.*/
  385. if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
  386. SKB_GSO_GRE_CSUM |
  387. SKB_GSO_UDP_TUNNEL |
  388. SKB_GSO_UDP_TUNNEL_CSUM)) {
  389. if ((!(skb_shinfo(skb)->gso_type &
  390. SKB_GSO_PARTIAL)) &&
  391. (skb_shinfo(skb)->gso_type &
  392. SKB_GSO_UDP_TUNNEL_CSUM)) {
  393. /* Software should clear the udp's checksum
  394. * field when tso is needed.
  395. */
  396. l4.udp->check = 0;
  397. }
  398. /* reset l3&l4 pointers from outer to inner headers */
  399. l3.hdr = skb_inner_network_header(skb);
  400. l4.hdr = skb_inner_transport_header(skb);
  401. /* Software should clear the IPv4's checksum field when
  402. * tso is needed.
  403. */
  404. if (l3.v4->version == 4)
  405. l3.v4->check = 0;
  406. }
  407. /* normal or tunnel packet*/
  408. l4_offset = l4.hdr - skb->data;
  409. hdr_len = (l4.tcp->doff * 4) + l4_offset;
  410. /* remove payload length from inner pseudo checksum when tso*/
  411. l4_paylen = skb->len - l4_offset;
  412. csum_replace_by_diff(&l4.tcp->check,
  413. (__force __wsum)htonl(l4_paylen));
  414. /* find the txbd field values */
  415. *paylen = skb->len - hdr_len;
  416. hnae3_set_bit(*type_cs_vlan_tso,
  417. HNS3_TXD_TSO_B, 1);
  418. /* get MSS for TSO */
  419. *mss = skb_shinfo(skb)->gso_size;
  420. return 0;
  421. }
  422. static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
  423. u8 *il4_proto)
  424. {
  425. union {
  426. struct iphdr *v4;
  427. struct ipv6hdr *v6;
  428. unsigned char *hdr;
  429. } l3;
  430. unsigned char *l4_hdr;
  431. unsigned char *exthdr;
  432. u8 l4_proto_tmp;
  433. __be16 frag_off;
  434. /* find outer header point */
  435. l3.hdr = skb_network_header(skb);
  436. l4_hdr = skb_transport_header(skb);
  437. if (skb->protocol == htons(ETH_P_IPV6)) {
  438. exthdr = l3.hdr + sizeof(*l3.v6);
  439. l4_proto_tmp = l3.v6->nexthdr;
  440. if (l4_hdr != exthdr)
  441. ipv6_skip_exthdr(skb, exthdr - skb->data,
  442. &l4_proto_tmp, &frag_off);
  443. } else if (skb->protocol == htons(ETH_P_IP)) {
  444. l4_proto_tmp = l3.v4->protocol;
  445. } else {
  446. return -EINVAL;
  447. }
  448. *ol4_proto = l4_proto_tmp;
  449. /* tunnel packet */
  450. if (!skb->encapsulation) {
  451. *il4_proto = 0;
  452. return 0;
  453. }
  454. /* find inner header point */
  455. l3.hdr = skb_inner_network_header(skb);
  456. l4_hdr = skb_inner_transport_header(skb);
  457. if (l3.v6->version == 6) {
  458. exthdr = l3.hdr + sizeof(*l3.v6);
  459. l4_proto_tmp = l3.v6->nexthdr;
  460. if (l4_hdr != exthdr)
  461. ipv6_skip_exthdr(skb, exthdr - skb->data,
  462. &l4_proto_tmp, &frag_off);
  463. } else if (l3.v4->version == 4) {
  464. l4_proto_tmp = l3.v4->protocol;
  465. }
  466. *il4_proto = l4_proto_tmp;
  467. return 0;
  468. }
  469. static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
  470. u8 il4_proto, u32 *type_cs_vlan_tso,
  471. u32 *ol_type_vlan_len_msec)
  472. {
  473. union {
  474. struct iphdr *v4;
  475. struct ipv6hdr *v6;
  476. unsigned char *hdr;
  477. } l3;
  478. union {
  479. struct tcphdr *tcp;
  480. struct udphdr *udp;
  481. struct gre_base_hdr *gre;
  482. unsigned char *hdr;
  483. } l4;
  484. unsigned char *l2_hdr;
  485. u8 l4_proto = ol4_proto;
  486. u32 ol2_len;
  487. u32 ol3_len;
  488. u32 ol4_len;
  489. u32 l2_len;
  490. u32 l3_len;
  491. l3.hdr = skb_network_header(skb);
  492. l4.hdr = skb_transport_header(skb);
  493. /* compute L2 header size for normal packet, defined in 2 Bytes */
  494. l2_len = l3.hdr - skb->data;
  495. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
  496. HNS3_TXD_L2LEN_S, l2_len >> 1);
  497. /* tunnel packet*/
  498. if (skb->encapsulation) {
  499. /* compute OL2 header size, defined in 2 Bytes */
  500. ol2_len = l2_len;
  501. hnae3_set_field(*ol_type_vlan_len_msec,
  502. HNS3_TXD_L2LEN_M,
  503. HNS3_TXD_L2LEN_S, ol2_len >> 1);
  504. /* compute OL3 header size, defined in 4 Bytes */
  505. ol3_len = l4.hdr - l3.hdr;
  506. hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
  507. HNS3_TXD_L3LEN_S, ol3_len >> 2);
  508. /* MAC in UDP, MAC in GRE (0x6558)*/
  509. if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
  510. /* switch MAC header ptr from outer to inner header.*/
  511. l2_hdr = skb_inner_mac_header(skb);
  512. /* compute OL4 header size, defined in 4 Bytes. */
  513. ol4_len = l2_hdr - l4.hdr;
  514. hnae3_set_field(*ol_type_vlan_len_msec,
  515. HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
  516. ol4_len >> 2);
  517. /* switch IP header ptr from outer to inner header */
  518. l3.hdr = skb_inner_network_header(skb);
  519. /* compute inner l2 header size, defined in 2 Bytes. */
  520. l2_len = l3.hdr - l2_hdr;
  521. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
  522. HNS3_TXD_L2LEN_S, l2_len >> 1);
  523. } else {
  524. /* skb packet types not supported by hardware,
  525. * txbd len fild doesn't be filled.
  526. */
  527. return;
  528. }
  529. /* switch L4 header pointer from outer to inner */
  530. l4.hdr = skb_inner_transport_header(skb);
  531. l4_proto = il4_proto;
  532. }
  533. /* compute inner(/normal) L3 header size, defined in 4 Bytes */
  534. l3_len = l4.hdr - l3.hdr;
  535. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
  536. HNS3_TXD_L3LEN_S, l3_len >> 2);
  537. /* compute inner(/normal) L4 header size, defined in 4 Bytes */
  538. switch (l4_proto) {
  539. case IPPROTO_TCP:
  540. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
  541. HNS3_TXD_L4LEN_S, l4.tcp->doff);
  542. break;
  543. case IPPROTO_SCTP:
  544. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
  545. HNS3_TXD_L4LEN_S,
  546. (sizeof(struct sctphdr) >> 2));
  547. break;
  548. case IPPROTO_UDP:
  549. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
  550. HNS3_TXD_L4LEN_S,
  551. (sizeof(struct udphdr) >> 2));
  552. break;
  553. default:
  554. /* skb packet types not supported by hardware,
  555. * txbd len fild doesn't be filled.
  556. */
  557. return;
  558. }
  559. }
  560. /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
  561. * and it is udp packet, which has a dest port as the IANA assigned.
  562. * the hardware is expected to do the checksum offload, but the
  563. * hardware will not do the checksum offload when udp dest port is
  564. * 4789.
  565. */
  566. static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
  567. {
  568. #define IANA_VXLAN_PORT 4789
  569. union {
  570. struct tcphdr *tcp;
  571. struct udphdr *udp;
  572. struct gre_base_hdr *gre;
  573. unsigned char *hdr;
  574. } l4;
  575. l4.hdr = skb_transport_header(skb);
  576. if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
  577. return false;
  578. skb_checksum_help(skb);
  579. return true;
  580. }
  581. static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
  582. u8 il4_proto, u32 *type_cs_vlan_tso,
  583. u32 *ol_type_vlan_len_msec)
  584. {
  585. union {
  586. struct iphdr *v4;
  587. struct ipv6hdr *v6;
  588. unsigned char *hdr;
  589. } l3;
  590. u32 l4_proto = ol4_proto;
  591. l3.hdr = skb_network_header(skb);
  592. /* define OL3 type and tunnel type(OL4).*/
  593. if (skb->encapsulation) {
  594. /* define outer network header type.*/
  595. if (skb->protocol == htons(ETH_P_IP)) {
  596. if (skb_is_gso(skb))
  597. hnae3_set_field(*ol_type_vlan_len_msec,
  598. HNS3_TXD_OL3T_M,
  599. HNS3_TXD_OL3T_S,
  600. HNS3_OL3T_IPV4_CSUM);
  601. else
  602. hnae3_set_field(*ol_type_vlan_len_msec,
  603. HNS3_TXD_OL3T_M,
  604. HNS3_TXD_OL3T_S,
  605. HNS3_OL3T_IPV4_NO_CSUM);
  606. } else if (skb->protocol == htons(ETH_P_IPV6)) {
  607. hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
  608. HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
  609. }
  610. /* define tunnel type(OL4).*/
  611. switch (l4_proto) {
  612. case IPPROTO_UDP:
  613. hnae3_set_field(*ol_type_vlan_len_msec,
  614. HNS3_TXD_TUNTYPE_M,
  615. HNS3_TXD_TUNTYPE_S,
  616. HNS3_TUN_MAC_IN_UDP);
  617. break;
  618. case IPPROTO_GRE:
  619. hnae3_set_field(*ol_type_vlan_len_msec,
  620. HNS3_TXD_TUNTYPE_M,
  621. HNS3_TXD_TUNTYPE_S,
  622. HNS3_TUN_NVGRE);
  623. break;
  624. default:
  625. /* drop the skb tunnel packet if hardware don't support,
  626. * because hardware can't calculate csum when TSO.
  627. */
  628. if (skb_is_gso(skb))
  629. return -EDOM;
  630. /* the stack computes the IP header already,
  631. * driver calculate l4 checksum when not TSO.
  632. */
  633. skb_checksum_help(skb);
  634. return 0;
  635. }
  636. l3.hdr = skb_inner_network_header(skb);
  637. l4_proto = il4_proto;
  638. }
  639. if (l3.v4->version == 4) {
  640. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
  641. HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
  642. /* the stack computes the IP header already, the only time we
  643. * need the hardware to recompute it is in the case of TSO.
  644. */
  645. if (skb_is_gso(skb))
  646. hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
  647. } else if (l3.v6->version == 6) {
  648. hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
  649. HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
  650. }
  651. switch (l4_proto) {
  652. case IPPROTO_TCP:
  653. hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
  654. hnae3_set_field(*type_cs_vlan_tso,
  655. HNS3_TXD_L4T_M,
  656. HNS3_TXD_L4T_S,
  657. HNS3_L4T_TCP);
  658. break;
  659. case IPPROTO_UDP:
  660. if (hns3_tunnel_csum_bug(skb))
  661. break;
  662. hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
  663. hnae3_set_field(*type_cs_vlan_tso,
  664. HNS3_TXD_L4T_M,
  665. HNS3_TXD_L4T_S,
  666. HNS3_L4T_UDP);
  667. break;
  668. case IPPROTO_SCTP:
  669. hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
  670. hnae3_set_field(*type_cs_vlan_tso,
  671. HNS3_TXD_L4T_M,
  672. HNS3_TXD_L4T_S,
  673. HNS3_L4T_SCTP);
  674. break;
  675. default:
  676. /* drop the skb tunnel packet if hardware don't support,
  677. * because hardware can't calculate csum when TSO.
  678. */
  679. if (skb_is_gso(skb))
  680. return -EDOM;
  681. /* the stack computes the IP header already,
  682. * driver calculate l4 checksum when not TSO.
  683. */
  684. skb_checksum_help(skb);
  685. return 0;
  686. }
  687. return 0;
  688. }
  689. static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
  690. {
  691. /* Config bd buffer end */
  692. hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
  693. HNS3_TXD_BDTYPE_S, 0);
  694. hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
  695. hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
  696. hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
  697. }
  698. static int hns3_fill_desc_vtags(struct sk_buff *skb,
  699. struct hns3_enet_ring *tx_ring,
  700. u32 *inner_vlan_flag,
  701. u32 *out_vlan_flag,
  702. u16 *inner_vtag,
  703. u16 *out_vtag)
  704. {
  705. #define HNS3_TX_VLAN_PRIO_SHIFT 13
  706. if (skb->protocol == htons(ETH_P_8021Q) &&
  707. !(tx_ring->tqp->handle->kinfo.netdev->features &
  708. NETIF_F_HW_VLAN_CTAG_TX)) {
  709. /* When HW VLAN acceleration is turned off, and the stack
  710. * sets the protocol to 802.1q, the driver just need to
  711. * set the protocol to the encapsulated ethertype.
  712. */
  713. skb->protocol = vlan_get_protocol(skb);
  714. return 0;
  715. }
  716. if (skb_vlan_tag_present(skb)) {
  717. u16 vlan_tag;
  718. vlan_tag = skb_vlan_tag_get(skb);
  719. vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
  720. /* Based on hw strategy, use out_vtag in two layer tag case,
  721. * and use inner_vtag in one tag case.
  722. */
  723. if (skb->protocol == htons(ETH_P_8021Q)) {
  724. hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
  725. *out_vtag = vlan_tag;
  726. } else {
  727. hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
  728. *inner_vtag = vlan_tag;
  729. }
  730. } else if (skb->protocol == htons(ETH_P_8021Q)) {
  731. struct vlan_ethhdr *vhdr;
  732. int rc;
  733. rc = skb_cow_head(skb, 0);
  734. if (rc < 0)
  735. return rc;
  736. vhdr = (struct vlan_ethhdr *)skb->data;
  737. vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
  738. << HNS3_TX_VLAN_PRIO_SHIFT);
  739. }
  740. skb->protocol = vlan_get_protocol(skb);
  741. return 0;
  742. }
  743. static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
  744. int size, dma_addr_t dma, int frag_end,
  745. enum hns_desc_type type)
  746. {
  747. struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
  748. struct hns3_desc *desc = &ring->desc[ring->next_to_use];
  749. u32 ol_type_vlan_len_msec = 0;
  750. u16 bdtp_fe_sc_vld_ra_ri = 0;
  751. u32 type_cs_vlan_tso = 0;
  752. struct sk_buff *skb;
  753. u16 inner_vtag = 0;
  754. u16 out_vtag = 0;
  755. u32 paylen = 0;
  756. u16 mss = 0;
  757. u8 ol4_proto;
  758. u8 il4_proto;
  759. int ret;
  760. /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
  761. desc_cb->priv = priv;
  762. desc_cb->length = size;
  763. desc_cb->dma = dma;
  764. desc_cb->type = type;
  765. /* now, fill the descriptor */
  766. desc->addr = cpu_to_le64(dma);
  767. desc->tx.send_size = cpu_to_le16((u16)size);
  768. hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
  769. desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
  770. if (type == DESC_TYPE_SKB) {
  771. skb = (struct sk_buff *)priv;
  772. paylen = skb->len;
  773. ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
  774. &ol_type_vlan_len_msec,
  775. &inner_vtag, &out_vtag);
  776. if (unlikely(ret))
  777. return ret;
  778. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  779. skb_reset_mac_len(skb);
  780. ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
  781. if (ret)
  782. return ret;
  783. hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
  784. &type_cs_vlan_tso,
  785. &ol_type_vlan_len_msec);
  786. ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
  787. &type_cs_vlan_tso,
  788. &ol_type_vlan_len_msec);
  789. if (ret)
  790. return ret;
  791. ret = hns3_set_tso(skb, &paylen, &mss,
  792. &type_cs_vlan_tso);
  793. if (ret)
  794. return ret;
  795. }
  796. /* Set txbd */
  797. desc->tx.ol_type_vlan_len_msec =
  798. cpu_to_le32(ol_type_vlan_len_msec);
  799. desc->tx.type_cs_vlan_tso_len =
  800. cpu_to_le32(type_cs_vlan_tso);
  801. desc->tx.paylen = cpu_to_le32(paylen);
  802. desc->tx.mss = cpu_to_le16(mss);
  803. desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
  804. desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
  805. }
  806. /* move ring pointer to next.*/
  807. ring_ptr_move_fw(ring, next_to_use);
  808. return 0;
  809. }
  810. static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
  811. int size, dma_addr_t dma, int frag_end,
  812. enum hns_desc_type type)
  813. {
  814. unsigned int frag_buf_num;
  815. unsigned int k;
  816. int sizeoflast;
  817. int ret;
  818. frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
  819. sizeoflast = size % HNS3_MAX_BD_SIZE;
  820. sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
  821. /* When the frag size is bigger than hardware, split this frag */
  822. for (k = 0; k < frag_buf_num; k++) {
  823. ret = hns3_fill_desc(ring, priv,
  824. (k == frag_buf_num - 1) ?
  825. sizeoflast : HNS3_MAX_BD_SIZE,
  826. dma + HNS3_MAX_BD_SIZE * k,
  827. frag_end && (k == frag_buf_num - 1) ? 1 : 0,
  828. (type == DESC_TYPE_SKB && !k) ?
  829. DESC_TYPE_SKB : DESC_TYPE_PAGE);
  830. if (ret)
  831. return ret;
  832. }
  833. return 0;
  834. }
  835. static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
  836. struct hns3_enet_ring *ring)
  837. {
  838. struct sk_buff *skb = *out_skb;
  839. struct skb_frag_struct *frag;
  840. int bdnum_for_frag;
  841. int frag_num;
  842. int buf_num;
  843. int size;
  844. int i;
  845. size = skb_headlen(skb);
  846. buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
  847. frag_num = skb_shinfo(skb)->nr_frags;
  848. for (i = 0; i < frag_num; i++) {
  849. frag = &skb_shinfo(skb)->frags[i];
  850. size = skb_frag_size(frag);
  851. bdnum_for_frag =
  852. (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
  853. if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
  854. return -ENOMEM;
  855. buf_num += bdnum_for_frag;
  856. }
  857. if (buf_num > ring_space(ring))
  858. return -EBUSY;
  859. *bnum = buf_num;
  860. return 0;
  861. }
  862. static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
  863. struct hns3_enet_ring *ring)
  864. {
  865. struct sk_buff *skb = *out_skb;
  866. int buf_num;
  867. /* No. of segments (plus a header) */
  868. buf_num = skb_shinfo(skb)->nr_frags + 1;
  869. if (buf_num > ring_space(ring))
  870. return -EBUSY;
  871. *bnum = buf_num;
  872. return 0;
  873. }
  874. static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
  875. {
  876. struct device *dev = ring_to_dev(ring);
  877. unsigned int i;
  878. for (i = 0; i < ring->desc_num; i++) {
  879. /* check if this is where we started */
  880. if (ring->next_to_use == next_to_use_orig)
  881. break;
  882. /* unmap the descriptor dma address */
  883. if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
  884. dma_unmap_single(dev,
  885. ring->desc_cb[ring->next_to_use].dma,
  886. ring->desc_cb[ring->next_to_use].length,
  887. DMA_TO_DEVICE);
  888. else
  889. dma_unmap_page(dev,
  890. ring->desc_cb[ring->next_to_use].dma,
  891. ring->desc_cb[ring->next_to_use].length,
  892. DMA_TO_DEVICE);
  893. /* rollback one */
  894. ring_ptr_move_bw(ring, next_to_use);
  895. }
  896. }
  897. netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
  898. {
  899. struct hns3_nic_priv *priv = netdev_priv(netdev);
  900. struct hns3_nic_ring_data *ring_data =
  901. &tx_ring_data(priv, skb->queue_mapping);
  902. struct hns3_enet_ring *ring = ring_data->ring;
  903. struct device *dev = priv->dev;
  904. struct netdev_queue *dev_queue;
  905. struct skb_frag_struct *frag;
  906. int next_to_use_head;
  907. int next_to_use_frag;
  908. dma_addr_t dma;
  909. int buf_num;
  910. int seg_num;
  911. int size;
  912. int ret;
  913. int i;
  914. /* Prefetch the data used later */
  915. prefetch(skb->data);
  916. switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
  917. case -EBUSY:
  918. u64_stats_update_begin(&ring->syncp);
  919. ring->stats.tx_busy++;
  920. u64_stats_update_end(&ring->syncp);
  921. goto out_net_tx_busy;
  922. case -ENOMEM:
  923. u64_stats_update_begin(&ring->syncp);
  924. ring->stats.sw_err_cnt++;
  925. u64_stats_update_end(&ring->syncp);
  926. netdev_err(netdev, "no memory to xmit!\n");
  927. goto out_err_tx_ok;
  928. default:
  929. break;
  930. }
  931. /* No. of segments (plus a header) */
  932. seg_num = skb_shinfo(skb)->nr_frags + 1;
  933. /* Fill the first part */
  934. size = skb_headlen(skb);
  935. next_to_use_head = ring->next_to_use;
  936. dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
  937. if (dma_mapping_error(dev, dma)) {
  938. netdev_err(netdev, "TX head DMA map failed\n");
  939. ring->stats.sw_err_cnt++;
  940. goto out_err_tx_ok;
  941. }
  942. ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
  943. DESC_TYPE_SKB);
  944. if (ret)
  945. goto head_dma_map_err;
  946. next_to_use_frag = ring->next_to_use;
  947. /* Fill the fragments */
  948. for (i = 1; i < seg_num; i++) {
  949. frag = &skb_shinfo(skb)->frags[i - 1];
  950. size = skb_frag_size(frag);
  951. dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
  952. if (dma_mapping_error(dev, dma)) {
  953. netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
  954. ring->stats.sw_err_cnt++;
  955. goto frag_dma_map_err;
  956. }
  957. ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
  958. seg_num - 1 == i ? 1 : 0,
  959. DESC_TYPE_PAGE);
  960. if (ret)
  961. goto frag_dma_map_err;
  962. }
  963. /* Complete translate all packets */
  964. dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
  965. netdev_tx_sent_queue(dev_queue, skb->len);
  966. wmb(); /* Commit all data before submit */
  967. hnae3_queue_xmit(ring->tqp, buf_num);
  968. return NETDEV_TX_OK;
  969. frag_dma_map_err:
  970. hns_nic_dma_unmap(ring, next_to_use_frag);
  971. head_dma_map_err:
  972. hns_nic_dma_unmap(ring, next_to_use_head);
  973. out_err_tx_ok:
  974. dev_kfree_skb_any(skb);
  975. return NETDEV_TX_OK;
  976. out_net_tx_busy:
  977. netif_stop_subqueue(netdev, ring_data->queue_index);
  978. smp_mb(); /* Commit all data before submit */
  979. return NETDEV_TX_BUSY;
  980. }
  981. static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
  982. {
  983. struct hnae3_handle *h = hns3_get_handle(netdev);
  984. struct sockaddr *mac_addr = p;
  985. int ret;
  986. if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
  987. return -EADDRNOTAVAIL;
  988. if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
  989. netdev_info(netdev, "already using mac address %pM\n",
  990. mac_addr->sa_data);
  991. return 0;
  992. }
  993. ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
  994. if (ret) {
  995. netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
  996. return ret;
  997. }
  998. ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
  999. return 0;
  1000. }
  1001. static int hns3_nic_set_features(struct net_device *netdev,
  1002. netdev_features_t features)
  1003. {
  1004. netdev_features_t changed = netdev->features ^ features;
  1005. struct hns3_nic_priv *priv = netdev_priv(netdev);
  1006. struct hnae3_handle *h = priv->ae_handle;
  1007. int ret;
  1008. if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
  1009. if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
  1010. priv->ops.fill_desc = hns3_fill_desc_tso;
  1011. priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
  1012. } else {
  1013. priv->ops.fill_desc = hns3_fill_desc;
  1014. priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
  1015. }
  1016. }
  1017. if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
  1018. h->ae_algo->ops->enable_vlan_filter) {
  1019. if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
  1020. h->ae_algo->ops->enable_vlan_filter(h, true);
  1021. else
  1022. h->ae_algo->ops->enable_vlan_filter(h, false);
  1023. }
  1024. if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
  1025. h->ae_algo->ops->enable_hw_strip_rxvtag) {
  1026. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1027. ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
  1028. else
  1029. ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
  1030. if (ret)
  1031. return ret;
  1032. }
  1033. netdev->features = features;
  1034. return 0;
  1035. }
  1036. static void hns3_nic_get_stats64(struct net_device *netdev,
  1037. struct rtnl_link_stats64 *stats)
  1038. {
  1039. struct hns3_nic_priv *priv = netdev_priv(netdev);
  1040. int queue_num = priv->ae_handle->kinfo.num_tqps;
  1041. struct hnae3_handle *handle = priv->ae_handle;
  1042. struct hns3_enet_ring *ring;
  1043. unsigned int start;
  1044. unsigned int idx;
  1045. u64 tx_bytes = 0;
  1046. u64 rx_bytes = 0;
  1047. u64 tx_pkts = 0;
  1048. u64 rx_pkts = 0;
  1049. u64 tx_drop = 0;
  1050. u64 rx_drop = 0;
  1051. if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
  1052. return;
  1053. handle->ae_algo->ops->update_stats(handle, &netdev->stats);
  1054. for (idx = 0; idx < queue_num; idx++) {
  1055. /* fetch the tx stats */
  1056. ring = priv->ring_data[idx].ring;
  1057. do {
  1058. start = u64_stats_fetch_begin_irq(&ring->syncp);
  1059. tx_bytes += ring->stats.tx_bytes;
  1060. tx_pkts += ring->stats.tx_pkts;
  1061. tx_drop += ring->stats.tx_busy;
  1062. tx_drop += ring->stats.sw_err_cnt;
  1063. } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
  1064. /* fetch the rx stats */
  1065. ring = priv->ring_data[idx + queue_num].ring;
  1066. do {
  1067. start = u64_stats_fetch_begin_irq(&ring->syncp);
  1068. rx_bytes += ring->stats.rx_bytes;
  1069. rx_pkts += ring->stats.rx_pkts;
  1070. rx_drop += ring->stats.non_vld_descs;
  1071. rx_drop += ring->stats.err_pkt_len;
  1072. rx_drop += ring->stats.l2_err;
  1073. } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
  1074. }
  1075. stats->tx_bytes = tx_bytes;
  1076. stats->tx_packets = tx_pkts;
  1077. stats->rx_bytes = rx_bytes;
  1078. stats->rx_packets = rx_pkts;
  1079. stats->rx_errors = netdev->stats.rx_errors;
  1080. stats->multicast = netdev->stats.multicast;
  1081. stats->rx_length_errors = netdev->stats.rx_length_errors;
  1082. stats->rx_crc_errors = netdev->stats.rx_crc_errors;
  1083. stats->rx_missed_errors = netdev->stats.rx_missed_errors;
  1084. stats->tx_errors = netdev->stats.tx_errors;
  1085. stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
  1086. stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
  1087. stats->collisions = netdev->stats.collisions;
  1088. stats->rx_over_errors = netdev->stats.rx_over_errors;
  1089. stats->rx_frame_errors = netdev->stats.rx_frame_errors;
  1090. stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
  1091. stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
  1092. stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
  1093. stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
  1094. stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
  1095. stats->tx_window_errors = netdev->stats.tx_window_errors;
  1096. stats->rx_compressed = netdev->stats.rx_compressed;
  1097. stats->tx_compressed = netdev->stats.tx_compressed;
  1098. }
  1099. static int hns3_setup_tc(struct net_device *netdev, void *type_data)
  1100. {
  1101. struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
  1102. struct hnae3_handle *h = hns3_get_handle(netdev);
  1103. struct hnae3_knic_private_info *kinfo = &h->kinfo;
  1104. u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
  1105. u8 tc = mqprio_qopt->qopt.num_tc;
  1106. u16 mode = mqprio_qopt->mode;
  1107. u8 hw = mqprio_qopt->qopt.hw;
  1108. bool if_running;
  1109. int ret;
  1110. if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
  1111. mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
  1112. return -EOPNOTSUPP;
  1113. if (tc > HNAE3_MAX_TC)
  1114. return -EINVAL;
  1115. if (!netdev)
  1116. return -EINVAL;
  1117. if_running = netif_running(netdev);
  1118. if (if_running) {
  1119. hns3_nic_net_stop(netdev);
  1120. msleep(100);
  1121. }
  1122. ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
  1123. kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
  1124. if (ret)
  1125. goto out;
  1126. ret = hns3_nic_set_real_num_queue(netdev);
  1127. out:
  1128. if (if_running)
  1129. hns3_nic_net_open(netdev);
  1130. return ret;
  1131. }
  1132. static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
  1133. void *type_data)
  1134. {
  1135. if (type != TC_SETUP_QDISC_MQPRIO)
  1136. return -EOPNOTSUPP;
  1137. return hns3_setup_tc(dev, type_data);
  1138. }
  1139. static int hns3_vlan_rx_add_vid(struct net_device *netdev,
  1140. __be16 proto, u16 vid)
  1141. {
  1142. struct hnae3_handle *h = hns3_get_handle(netdev);
  1143. struct hns3_nic_priv *priv = netdev_priv(netdev);
  1144. int ret = -EIO;
  1145. if (h->ae_algo->ops->set_vlan_filter)
  1146. ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
  1147. if (!ret)
  1148. set_bit(vid, priv->active_vlans);
  1149. return ret;
  1150. }
  1151. static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
  1152. __be16 proto, u16 vid)
  1153. {
  1154. struct hnae3_handle *h = hns3_get_handle(netdev);
  1155. struct hns3_nic_priv *priv = netdev_priv(netdev);
  1156. int ret = -EIO;
  1157. if (h->ae_algo->ops->set_vlan_filter)
  1158. ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
  1159. if (!ret)
  1160. clear_bit(vid, priv->active_vlans);
  1161. return ret;
  1162. }
  1163. static void hns3_restore_vlan(struct net_device *netdev)
  1164. {
  1165. struct hns3_nic_priv *priv = netdev_priv(netdev);
  1166. u16 vid;
  1167. int ret;
  1168. for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
  1169. ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
  1170. if (ret)
  1171. netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
  1172. vid, ret);
  1173. }
  1174. }
  1175. static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
  1176. u8 qos, __be16 vlan_proto)
  1177. {
  1178. struct hnae3_handle *h = hns3_get_handle(netdev);
  1179. int ret = -EIO;
  1180. if (h->ae_algo->ops->set_vf_vlan_filter)
  1181. ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
  1182. qos, vlan_proto);
  1183. return ret;
  1184. }
  1185. static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
  1186. {
  1187. struct hnae3_handle *h = hns3_get_handle(netdev);
  1188. bool if_running = netif_running(netdev);
  1189. int ret;
  1190. if (!h->ae_algo->ops->set_mtu)
  1191. return -EOPNOTSUPP;
  1192. /* if this was called with netdev up then bring netdevice down */
  1193. if (if_running) {
  1194. (void)hns3_nic_net_stop(netdev);
  1195. msleep(100);
  1196. }
  1197. ret = h->ae_algo->ops->set_mtu(h, new_mtu);
  1198. if (ret)
  1199. netdev_err(netdev, "failed to change MTU in hardware %d\n",
  1200. ret);
  1201. else
  1202. netdev->mtu = new_mtu;
  1203. /* if the netdev was running earlier, bring it up again */
  1204. if (if_running && hns3_nic_net_open(netdev))
  1205. ret = -EINVAL;
  1206. return ret;
  1207. }
  1208. static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
  1209. {
  1210. struct hns3_nic_priv *priv = netdev_priv(ndev);
  1211. struct hns3_enet_ring *tx_ring = NULL;
  1212. int timeout_queue = 0;
  1213. int hw_head, hw_tail;
  1214. int i;
  1215. /* Find the stopped queue the same way the stack does */
  1216. for (i = 0; i < ndev->num_tx_queues; i++) {
  1217. struct netdev_queue *q;
  1218. unsigned long trans_start;
  1219. q = netdev_get_tx_queue(ndev, i);
  1220. trans_start = q->trans_start;
  1221. if (netif_xmit_stopped(q) &&
  1222. time_after(jiffies,
  1223. (trans_start + ndev->watchdog_timeo))) {
  1224. timeout_queue = i;
  1225. netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
  1226. q->state,
  1227. jiffies_to_msecs(jiffies - trans_start));
  1228. break;
  1229. }
  1230. }
  1231. if (i == ndev->num_tx_queues) {
  1232. netdev_info(ndev,
  1233. "no netdev TX timeout queue found, timeout count: %llu\n",
  1234. priv->tx_timeout_count);
  1235. return false;
  1236. }
  1237. tx_ring = priv->ring_data[timeout_queue].ring;
  1238. hw_head = readl_relaxed(tx_ring->tqp->io_base +
  1239. HNS3_RING_TX_RING_HEAD_REG);
  1240. hw_tail = readl_relaxed(tx_ring->tqp->io_base +
  1241. HNS3_RING_TX_RING_TAIL_REG);
  1242. netdev_info(ndev,
  1243. "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
  1244. priv->tx_timeout_count,
  1245. timeout_queue,
  1246. tx_ring->next_to_use,
  1247. tx_ring->next_to_clean,
  1248. hw_head,
  1249. hw_tail,
  1250. readl(tx_ring->tqp_vector->mask_addr));
  1251. return true;
  1252. }
  1253. static void hns3_nic_net_timeout(struct net_device *ndev)
  1254. {
  1255. struct hns3_nic_priv *priv = netdev_priv(ndev);
  1256. struct hnae3_handle *h = priv->ae_handle;
  1257. if (!hns3_get_tx_timeo_queue_info(ndev))
  1258. return;
  1259. priv->tx_timeout_count++;
  1260. if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
  1261. return;
  1262. /* request the reset */
  1263. if (h->ae_algo->ops->reset_event)
  1264. h->ae_algo->ops->reset_event(h);
  1265. }
  1266. static const struct net_device_ops hns3_nic_netdev_ops = {
  1267. .ndo_open = hns3_nic_net_open,
  1268. .ndo_stop = hns3_nic_net_stop,
  1269. .ndo_start_xmit = hns3_nic_net_xmit,
  1270. .ndo_tx_timeout = hns3_nic_net_timeout,
  1271. .ndo_set_mac_address = hns3_nic_net_set_mac_address,
  1272. .ndo_change_mtu = hns3_nic_change_mtu,
  1273. .ndo_set_features = hns3_nic_set_features,
  1274. .ndo_get_stats64 = hns3_nic_get_stats64,
  1275. .ndo_setup_tc = hns3_nic_setup_tc,
  1276. .ndo_set_rx_mode = hns3_nic_set_rx_mode,
  1277. .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
  1278. .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
  1279. .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
  1280. };
  1281. static bool hns3_is_phys_func(struct pci_dev *pdev)
  1282. {
  1283. u32 dev_id = pdev->device;
  1284. switch (dev_id) {
  1285. case HNAE3_DEV_ID_GE:
  1286. case HNAE3_DEV_ID_25GE:
  1287. case HNAE3_DEV_ID_25GE_RDMA:
  1288. case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
  1289. case HNAE3_DEV_ID_50GE_RDMA:
  1290. case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
  1291. case HNAE3_DEV_ID_100G_RDMA_MACSEC:
  1292. return true;
  1293. case HNAE3_DEV_ID_100G_VF:
  1294. case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
  1295. return false;
  1296. default:
  1297. dev_warn(&pdev->dev, "un-recognized pci device-id %d",
  1298. dev_id);
  1299. }
  1300. return false;
  1301. }
  1302. static void hns3_disable_sriov(struct pci_dev *pdev)
  1303. {
  1304. /* If our VFs are assigned we cannot shut down SR-IOV
  1305. * without causing issues, so just leave the hardware
  1306. * available but disabled
  1307. */
  1308. if (pci_vfs_assigned(pdev)) {
  1309. dev_warn(&pdev->dev,
  1310. "disabling driver while VFs are assigned\n");
  1311. return;
  1312. }
  1313. pci_disable_sriov(pdev);
  1314. }
  1315. /* hns3_probe - Device initialization routine
  1316. * @pdev: PCI device information struct
  1317. * @ent: entry in hns3_pci_tbl
  1318. *
  1319. * hns3_probe initializes a PF identified by a pci_dev structure.
  1320. * The OS initialization, configuring of the PF private structure,
  1321. * and a hardware reset occur.
  1322. *
  1323. * Returns 0 on success, negative on failure
  1324. */
  1325. static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1326. {
  1327. struct hnae3_ae_dev *ae_dev;
  1328. int ret;
  1329. ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
  1330. GFP_KERNEL);
  1331. if (!ae_dev) {
  1332. ret = -ENOMEM;
  1333. return ret;
  1334. }
  1335. ae_dev->pdev = pdev;
  1336. ae_dev->flag = ent->driver_data;
  1337. ae_dev->dev_type = HNAE3_DEV_KNIC;
  1338. pci_set_drvdata(pdev, ae_dev);
  1339. ret = hnae3_register_ae_dev(ae_dev);
  1340. if (ret) {
  1341. devm_kfree(&pdev->dev, ae_dev);
  1342. pci_set_drvdata(pdev, NULL);
  1343. }
  1344. return ret;
  1345. }
  1346. /* hns3_remove - Device removal routine
  1347. * @pdev: PCI device information struct
  1348. */
  1349. static void hns3_remove(struct pci_dev *pdev)
  1350. {
  1351. struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
  1352. if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
  1353. hns3_disable_sriov(pdev);
  1354. hnae3_unregister_ae_dev(ae_dev);
  1355. pci_set_drvdata(pdev, NULL);
  1356. }
  1357. /**
  1358. * hns3_pci_sriov_configure
  1359. * @pdev: pointer to a pci_dev structure
  1360. * @num_vfs: number of VFs to allocate
  1361. *
  1362. * Enable or change the number of VFs. Called when the user updates the number
  1363. * of VFs in sysfs.
  1364. **/
  1365. static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
  1366. {
  1367. int ret;
  1368. if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
  1369. dev_warn(&pdev->dev, "Can not config SRIOV\n");
  1370. return -EINVAL;
  1371. }
  1372. if (num_vfs) {
  1373. ret = pci_enable_sriov(pdev, num_vfs);
  1374. if (ret)
  1375. dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
  1376. else
  1377. return num_vfs;
  1378. } else if (!pci_vfs_assigned(pdev)) {
  1379. pci_disable_sriov(pdev);
  1380. } else {
  1381. dev_warn(&pdev->dev,
  1382. "Unable to free VFs because some are assigned to VMs.\n");
  1383. }
  1384. return 0;
  1385. }
  1386. static struct pci_driver hns3_driver = {
  1387. .name = hns3_driver_name,
  1388. .id_table = hns3_pci_tbl,
  1389. .probe = hns3_probe,
  1390. .remove = hns3_remove,
  1391. .sriov_configure = hns3_pci_sriov_configure,
  1392. };
  1393. /* set default feature to hns3 */
  1394. static void hns3_set_default_feature(struct net_device *netdev)
  1395. {
  1396. struct hnae3_handle *h = hns3_get_handle(netdev);
  1397. struct pci_dev *pdev = h->pdev;
  1398. netdev->priv_flags |= IFF_UNICAST_FLT;
  1399. netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1400. NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
  1401. NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
  1402. NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
  1403. NETIF_F_GSO_UDP_TUNNEL_CSUM;
  1404. netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
  1405. netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
  1406. netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1407. NETIF_F_HW_VLAN_CTAG_FILTER |
  1408. NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
  1409. NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
  1410. NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
  1411. NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
  1412. NETIF_F_GSO_UDP_TUNNEL_CSUM;
  1413. netdev->vlan_features |=
  1414. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
  1415. NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
  1416. NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
  1417. NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
  1418. NETIF_F_GSO_UDP_TUNNEL_CSUM;
  1419. netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1420. NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
  1421. NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
  1422. NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
  1423. NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
  1424. NETIF_F_GSO_UDP_TUNNEL_CSUM;
  1425. if (pdev->revision != 0x20)
  1426. netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
  1427. }
  1428. static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
  1429. struct hns3_desc_cb *cb)
  1430. {
  1431. unsigned int order = hnae3_page_order(ring);
  1432. struct page *p;
  1433. p = dev_alloc_pages(order);
  1434. if (!p)
  1435. return -ENOMEM;
  1436. cb->priv = p;
  1437. cb->page_offset = 0;
  1438. cb->reuse_flag = 0;
  1439. cb->buf = page_address(p);
  1440. cb->length = hnae3_page_size(ring);
  1441. cb->type = DESC_TYPE_PAGE;
  1442. return 0;
  1443. }
  1444. static void hns3_free_buffer(struct hns3_enet_ring *ring,
  1445. struct hns3_desc_cb *cb)
  1446. {
  1447. if (cb->type == DESC_TYPE_SKB)
  1448. dev_kfree_skb_any((struct sk_buff *)cb->priv);
  1449. else if (!HNAE3_IS_TX_RING(ring))
  1450. put_page((struct page *)cb->priv);
  1451. memset(cb, 0, sizeof(*cb));
  1452. }
  1453. static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
  1454. {
  1455. cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
  1456. cb->length, ring_to_dma_dir(ring));
  1457. if (dma_mapping_error(ring_to_dev(ring), cb->dma))
  1458. return -EIO;
  1459. return 0;
  1460. }
  1461. static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
  1462. struct hns3_desc_cb *cb)
  1463. {
  1464. if (cb->type == DESC_TYPE_SKB)
  1465. dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
  1466. ring_to_dma_dir(ring));
  1467. else
  1468. dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
  1469. ring_to_dma_dir(ring));
  1470. }
  1471. static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
  1472. {
  1473. hns3_unmap_buffer(ring, &ring->desc_cb[i]);
  1474. ring->desc[i].addr = 0;
  1475. }
  1476. static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
  1477. {
  1478. struct hns3_desc_cb *cb = &ring->desc_cb[i];
  1479. if (!ring->desc_cb[i].dma)
  1480. return;
  1481. hns3_buffer_detach(ring, i);
  1482. hns3_free_buffer(ring, cb);
  1483. }
  1484. static void hns3_free_buffers(struct hns3_enet_ring *ring)
  1485. {
  1486. int i;
  1487. for (i = 0; i < ring->desc_num; i++)
  1488. hns3_free_buffer_detach(ring, i);
  1489. }
  1490. /* free desc along with its attached buffer */
  1491. static void hns3_free_desc(struct hns3_enet_ring *ring)
  1492. {
  1493. int size = ring->desc_num * sizeof(ring->desc[0]);
  1494. hns3_free_buffers(ring);
  1495. if (ring->desc) {
  1496. dma_free_coherent(ring_to_dev(ring), size,
  1497. ring->desc, ring->desc_dma_addr);
  1498. ring->desc = NULL;
  1499. }
  1500. }
  1501. static int hns3_alloc_desc(struct hns3_enet_ring *ring)
  1502. {
  1503. int size = ring->desc_num * sizeof(ring->desc[0]);
  1504. ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
  1505. &ring->desc_dma_addr,
  1506. GFP_KERNEL);
  1507. if (!ring->desc)
  1508. return -ENOMEM;
  1509. return 0;
  1510. }
  1511. static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
  1512. struct hns3_desc_cb *cb)
  1513. {
  1514. int ret;
  1515. ret = hns3_alloc_buffer(ring, cb);
  1516. if (ret)
  1517. goto out;
  1518. ret = hns3_map_buffer(ring, cb);
  1519. if (ret)
  1520. goto out_with_buf;
  1521. return 0;
  1522. out_with_buf:
  1523. hns3_free_buffer(ring, cb);
  1524. out:
  1525. return ret;
  1526. }
  1527. static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
  1528. {
  1529. int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
  1530. if (ret)
  1531. return ret;
  1532. ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
  1533. return 0;
  1534. }
  1535. /* Allocate memory for raw pkg, and map with dma */
  1536. static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
  1537. {
  1538. int i, j, ret;
  1539. for (i = 0; i < ring->desc_num; i++) {
  1540. ret = hns3_alloc_buffer_attach(ring, i);
  1541. if (ret)
  1542. goto out_buffer_fail;
  1543. }
  1544. return 0;
  1545. out_buffer_fail:
  1546. for (j = i - 1; j >= 0; j--)
  1547. hns3_free_buffer_detach(ring, j);
  1548. return ret;
  1549. }
  1550. /* detach a in-used buffer and replace with a reserved one */
  1551. static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
  1552. struct hns3_desc_cb *res_cb)
  1553. {
  1554. hns3_unmap_buffer(ring, &ring->desc_cb[i]);
  1555. ring->desc_cb[i] = *res_cb;
  1556. ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
  1557. ring->desc[i].rx.bd_base_info = 0;
  1558. }
  1559. static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
  1560. {
  1561. ring->desc_cb[i].reuse_flag = 0;
  1562. ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
  1563. + ring->desc_cb[i].page_offset);
  1564. ring->desc[i].rx.bd_base_info = 0;
  1565. }
  1566. static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
  1567. int *pkts)
  1568. {
  1569. struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
  1570. (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
  1571. (*bytes) += desc_cb->length;
  1572. /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
  1573. hns3_free_buffer_detach(ring, ring->next_to_clean);
  1574. ring_ptr_move_fw(ring, next_to_clean);
  1575. }
  1576. static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
  1577. {
  1578. int u = ring->next_to_use;
  1579. int c = ring->next_to_clean;
  1580. if (unlikely(h > ring->desc_num))
  1581. return 0;
  1582. return u > c ? (h > c && h <= u) : (h > c || h <= u);
  1583. }
  1584. bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
  1585. {
  1586. struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
  1587. struct hns3_nic_priv *priv = netdev_priv(netdev);
  1588. struct netdev_queue *dev_queue;
  1589. int bytes, pkts;
  1590. int head;
  1591. head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
  1592. rmb(); /* Make sure head is ready before touch any data */
  1593. if (is_ring_empty(ring) || head == ring->next_to_clean)
  1594. return true; /* no data to poll */
  1595. if (unlikely(!is_valid_clean_head(ring, head))) {
  1596. netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
  1597. ring->next_to_use, ring->next_to_clean);
  1598. u64_stats_update_begin(&ring->syncp);
  1599. ring->stats.io_err_cnt++;
  1600. u64_stats_update_end(&ring->syncp);
  1601. return true;
  1602. }
  1603. bytes = 0;
  1604. pkts = 0;
  1605. while (head != ring->next_to_clean && budget) {
  1606. hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
  1607. /* Issue prefetch for next Tx descriptor */
  1608. prefetch(&ring->desc_cb[ring->next_to_clean]);
  1609. budget--;
  1610. }
  1611. ring->tqp_vector->tx_group.total_bytes += bytes;
  1612. ring->tqp_vector->tx_group.total_packets += pkts;
  1613. u64_stats_update_begin(&ring->syncp);
  1614. ring->stats.tx_bytes += bytes;
  1615. ring->stats.tx_pkts += pkts;
  1616. u64_stats_update_end(&ring->syncp);
  1617. dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
  1618. netdev_tx_completed_queue(dev_queue, pkts, bytes);
  1619. if (unlikely(pkts && netif_carrier_ok(netdev) &&
  1620. (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
  1621. /* Make sure that anybody stopping the queue after this
  1622. * sees the new next_to_clean.
  1623. */
  1624. smp_mb();
  1625. if (netif_tx_queue_stopped(dev_queue) &&
  1626. !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
  1627. netif_tx_wake_queue(dev_queue);
  1628. ring->stats.restart_queue++;
  1629. }
  1630. }
  1631. return !!budget;
  1632. }
  1633. static int hns3_desc_unused(struct hns3_enet_ring *ring)
  1634. {
  1635. int ntc = ring->next_to_clean;
  1636. int ntu = ring->next_to_use;
  1637. return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
  1638. }
  1639. static void
  1640. hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
  1641. {
  1642. struct hns3_desc_cb *desc_cb;
  1643. struct hns3_desc_cb res_cbs;
  1644. int i, ret;
  1645. for (i = 0; i < cleand_count; i++) {
  1646. desc_cb = &ring->desc_cb[ring->next_to_use];
  1647. if (desc_cb->reuse_flag) {
  1648. u64_stats_update_begin(&ring->syncp);
  1649. ring->stats.reuse_pg_cnt++;
  1650. u64_stats_update_end(&ring->syncp);
  1651. hns3_reuse_buffer(ring, ring->next_to_use);
  1652. } else {
  1653. ret = hns3_reserve_buffer_map(ring, &res_cbs);
  1654. if (ret) {
  1655. u64_stats_update_begin(&ring->syncp);
  1656. ring->stats.sw_err_cnt++;
  1657. u64_stats_update_end(&ring->syncp);
  1658. netdev_err(ring->tqp->handle->kinfo.netdev,
  1659. "hnae reserve buffer map failed.\n");
  1660. break;
  1661. }
  1662. hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
  1663. }
  1664. ring_ptr_move_fw(ring, next_to_use);
  1665. }
  1666. wmb(); /* Make all data has been write before submit */
  1667. writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
  1668. }
  1669. static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
  1670. struct hns3_enet_ring *ring, int pull_len,
  1671. struct hns3_desc_cb *desc_cb)
  1672. {
  1673. struct hns3_desc *desc;
  1674. u32 truesize;
  1675. int size;
  1676. int last_offset;
  1677. bool twobufs;
  1678. twobufs = ((PAGE_SIZE < 8192) &&
  1679. hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
  1680. desc = &ring->desc[ring->next_to_clean];
  1681. size = le16_to_cpu(desc->rx.size);
  1682. truesize = hnae3_buf_size(ring);
  1683. if (!twobufs)
  1684. last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
  1685. skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
  1686. size - pull_len, truesize);
  1687. /* Avoid re-using remote pages,flag default unreuse */
  1688. if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
  1689. return;
  1690. if (twobufs) {
  1691. /* If we are only owner of page we can reuse it */
  1692. if (likely(page_count(desc_cb->priv) == 1)) {
  1693. /* Flip page offset to other buffer */
  1694. desc_cb->page_offset ^= truesize;
  1695. desc_cb->reuse_flag = 1;
  1696. /* bump ref count on page before it is given*/
  1697. get_page(desc_cb->priv);
  1698. }
  1699. return;
  1700. }
  1701. /* Move offset up to the next cache line */
  1702. desc_cb->page_offset += truesize;
  1703. if (desc_cb->page_offset <= last_offset) {
  1704. desc_cb->reuse_flag = 1;
  1705. /* Bump ref count on page before it is given*/
  1706. get_page(desc_cb->priv);
  1707. }
  1708. }
  1709. static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
  1710. struct hns3_desc *desc)
  1711. {
  1712. struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
  1713. int l3_type, l4_type;
  1714. u32 bd_base_info;
  1715. int ol4_type;
  1716. u32 l234info;
  1717. bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
  1718. l234info = le32_to_cpu(desc->rx.l234_info);
  1719. skb->ip_summed = CHECKSUM_NONE;
  1720. skb_checksum_none_assert(skb);
  1721. if (!(netdev->features & NETIF_F_RXCSUM))
  1722. return;
  1723. /* check if hardware has done checksum */
  1724. if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
  1725. return;
  1726. if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
  1727. hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
  1728. hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
  1729. hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
  1730. netdev_err(netdev, "L3/L4 error pkt\n");
  1731. u64_stats_update_begin(&ring->syncp);
  1732. ring->stats.l3l4_csum_err++;
  1733. u64_stats_update_end(&ring->syncp);
  1734. return;
  1735. }
  1736. l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
  1737. HNS3_RXD_L3ID_S);
  1738. l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
  1739. HNS3_RXD_L4ID_S);
  1740. ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
  1741. HNS3_RXD_OL4ID_S);
  1742. switch (ol4_type) {
  1743. case HNS3_OL4_TYPE_MAC_IN_UDP:
  1744. case HNS3_OL4_TYPE_NVGRE:
  1745. skb->csum_level = 1;
  1746. /* fall through */
  1747. case HNS3_OL4_TYPE_NO_TUN:
  1748. /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
  1749. if ((l3_type == HNS3_L3_TYPE_IPV4 ||
  1750. l3_type == HNS3_L3_TYPE_IPV6) &&
  1751. (l4_type == HNS3_L4_TYPE_UDP ||
  1752. l4_type == HNS3_L4_TYPE_TCP ||
  1753. l4_type == HNS3_L4_TYPE_SCTP))
  1754. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1755. break;
  1756. }
  1757. }
  1758. static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
  1759. {
  1760. napi_gro_receive(&ring->tqp_vector->napi, skb);
  1761. }
  1762. static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
  1763. struct hns3_desc *desc, u32 l234info,
  1764. u16 *vlan_tag)
  1765. {
  1766. struct pci_dev *pdev = ring->tqp->handle->pdev;
  1767. if (pdev->revision == 0x20) {
  1768. *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
  1769. if (!(*vlan_tag & VLAN_VID_MASK))
  1770. *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
  1771. return (*vlan_tag != 0);
  1772. }
  1773. #define HNS3_STRP_OUTER_VLAN 0x1
  1774. #define HNS3_STRP_INNER_VLAN 0x2
  1775. switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
  1776. HNS3_RXD_STRP_TAGP_S)) {
  1777. case HNS3_STRP_OUTER_VLAN:
  1778. *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
  1779. return true;
  1780. case HNS3_STRP_INNER_VLAN:
  1781. *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
  1782. return true;
  1783. default:
  1784. return false;
  1785. }
  1786. }
  1787. static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
  1788. struct sk_buff **out_skb, int *out_bnum)
  1789. {
  1790. struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
  1791. struct hns3_desc_cb *desc_cb;
  1792. struct hns3_desc *desc;
  1793. struct sk_buff *skb;
  1794. unsigned char *va;
  1795. u32 bd_base_info;
  1796. int pull_len;
  1797. u32 l234info;
  1798. int length;
  1799. int bnum;
  1800. desc = &ring->desc[ring->next_to_clean];
  1801. desc_cb = &ring->desc_cb[ring->next_to_clean];
  1802. prefetch(desc);
  1803. length = le16_to_cpu(desc->rx.size);
  1804. bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
  1805. /* Check valid BD */
  1806. if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
  1807. return -EFAULT;
  1808. va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
  1809. /* Prefetch first cache line of first page
  1810. * Idea is to cache few bytes of the header of the packet. Our L1 Cache
  1811. * line size is 64B so need to prefetch twice to make it 128B. But in
  1812. * actual we can have greater size of caches with 128B Level 1 cache
  1813. * lines. In such a case, single fetch would suffice to cache in the
  1814. * relevant part of the header.
  1815. */
  1816. prefetch(va);
  1817. #if L1_CACHE_BYTES < 128
  1818. prefetch(va + L1_CACHE_BYTES);
  1819. #endif
  1820. skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
  1821. HNS3_RX_HEAD_SIZE);
  1822. if (unlikely(!skb)) {
  1823. netdev_err(netdev, "alloc rx skb fail\n");
  1824. u64_stats_update_begin(&ring->syncp);
  1825. ring->stats.sw_err_cnt++;
  1826. u64_stats_update_end(&ring->syncp);
  1827. return -ENOMEM;
  1828. }
  1829. prefetchw(skb->data);
  1830. bnum = 1;
  1831. if (length <= HNS3_RX_HEAD_SIZE) {
  1832. memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
  1833. /* We can reuse buffer as-is, just make sure it is local */
  1834. if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
  1835. desc_cb->reuse_flag = 1;
  1836. else /* This page cannot be reused so discard it */
  1837. put_page(desc_cb->priv);
  1838. ring_ptr_move_fw(ring, next_to_clean);
  1839. } else {
  1840. u64_stats_update_begin(&ring->syncp);
  1841. ring->stats.seg_pkt_cnt++;
  1842. u64_stats_update_end(&ring->syncp);
  1843. pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
  1844. memcpy(__skb_put(skb, pull_len), va,
  1845. ALIGN(pull_len, sizeof(long)));
  1846. hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
  1847. ring_ptr_move_fw(ring, next_to_clean);
  1848. while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
  1849. desc = &ring->desc[ring->next_to_clean];
  1850. desc_cb = &ring->desc_cb[ring->next_to_clean];
  1851. bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
  1852. hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
  1853. ring_ptr_move_fw(ring, next_to_clean);
  1854. bnum++;
  1855. }
  1856. }
  1857. *out_bnum = bnum;
  1858. l234info = le32_to_cpu(desc->rx.l234_info);
  1859. /* Based on hw strategy, the tag offloaded will be stored at
  1860. * ot_vlan_tag in two layer tag case, and stored at vlan_tag
  1861. * in one layer tag case.
  1862. */
  1863. if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
  1864. u16 vlan_tag;
  1865. if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
  1866. __vlan_hwaccel_put_tag(skb,
  1867. htons(ETH_P_8021Q),
  1868. vlan_tag);
  1869. }
  1870. if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
  1871. netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
  1872. ((u64 *)desc)[0], ((u64 *)desc)[1]);
  1873. u64_stats_update_begin(&ring->syncp);
  1874. ring->stats.non_vld_descs++;
  1875. u64_stats_update_end(&ring->syncp);
  1876. dev_kfree_skb_any(skb);
  1877. return -EINVAL;
  1878. }
  1879. if (unlikely((!desc->rx.pkt_len) ||
  1880. hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
  1881. netdev_err(netdev, "truncated pkt\n");
  1882. u64_stats_update_begin(&ring->syncp);
  1883. ring->stats.err_pkt_len++;
  1884. u64_stats_update_end(&ring->syncp);
  1885. dev_kfree_skb_any(skb);
  1886. return -EFAULT;
  1887. }
  1888. if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
  1889. netdev_err(netdev, "L2 error pkt\n");
  1890. u64_stats_update_begin(&ring->syncp);
  1891. ring->stats.l2_err++;
  1892. u64_stats_update_end(&ring->syncp);
  1893. dev_kfree_skb_any(skb);
  1894. return -EFAULT;
  1895. }
  1896. u64_stats_update_begin(&ring->syncp);
  1897. ring->stats.rx_pkts++;
  1898. ring->stats.rx_bytes += skb->len;
  1899. u64_stats_update_end(&ring->syncp);
  1900. ring->tqp_vector->rx_group.total_bytes += skb->len;
  1901. hns3_rx_checksum(ring, skb, desc);
  1902. return 0;
  1903. }
  1904. int hns3_clean_rx_ring(
  1905. struct hns3_enet_ring *ring, int budget,
  1906. void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
  1907. {
  1908. #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
  1909. struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
  1910. int recv_pkts, recv_bds, clean_count, err;
  1911. int unused_count = hns3_desc_unused(ring);
  1912. struct sk_buff *skb = NULL;
  1913. int num, bnum = 0;
  1914. num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
  1915. rmb(); /* Make sure num taken effect before the other data is touched */
  1916. recv_pkts = 0, recv_bds = 0, clean_count = 0;
  1917. num -= unused_count;
  1918. while (recv_pkts < budget && recv_bds < num) {
  1919. /* Reuse or realloc buffers */
  1920. if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
  1921. hns3_nic_alloc_rx_buffers(ring,
  1922. clean_count + unused_count);
  1923. clean_count = 0;
  1924. unused_count = hns3_desc_unused(ring);
  1925. }
  1926. /* Poll one pkt */
  1927. err = hns3_handle_rx_bd(ring, &skb, &bnum);
  1928. if (unlikely(!skb)) /* This fault cannot be repaired */
  1929. goto out;
  1930. recv_bds += bnum;
  1931. clean_count += bnum;
  1932. if (unlikely(err)) { /* Do jump the err */
  1933. recv_pkts++;
  1934. continue;
  1935. }
  1936. /* Do update ip stack process */
  1937. skb->protocol = eth_type_trans(skb, netdev);
  1938. rx_fn(ring, skb);
  1939. recv_pkts++;
  1940. }
  1941. out:
  1942. /* Make all data has been write before submit */
  1943. if (clean_count + unused_count > 0)
  1944. hns3_nic_alloc_rx_buffers(ring,
  1945. clean_count + unused_count);
  1946. return recv_pkts;
  1947. }
  1948. static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
  1949. {
  1950. struct hns3_enet_tqp_vector *tqp_vector =
  1951. ring_group->ring->tqp_vector;
  1952. enum hns3_flow_level_range new_flow_level;
  1953. int packets_per_msecs;
  1954. int bytes_per_msecs;
  1955. u32 time_passed_ms;
  1956. u16 new_int_gl;
  1957. if (!tqp_vector->last_jiffies)
  1958. return false;
  1959. if (ring_group->total_packets == 0) {
  1960. ring_group->coal.int_gl = HNS3_INT_GL_50K;
  1961. ring_group->coal.flow_level = HNS3_FLOW_LOW;
  1962. return true;
  1963. }
  1964. /* Simple throttlerate management
  1965. * 0-10MB/s lower (50000 ints/s)
  1966. * 10-20MB/s middle (20000 ints/s)
  1967. * 20-1249MB/s high (18000 ints/s)
  1968. * > 40000pps ultra (8000 ints/s)
  1969. */
  1970. new_flow_level = ring_group->coal.flow_level;
  1971. new_int_gl = ring_group->coal.int_gl;
  1972. time_passed_ms =
  1973. jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
  1974. if (!time_passed_ms)
  1975. return false;
  1976. do_div(ring_group->total_packets, time_passed_ms);
  1977. packets_per_msecs = ring_group->total_packets;
  1978. do_div(ring_group->total_bytes, time_passed_ms);
  1979. bytes_per_msecs = ring_group->total_bytes;
  1980. #define HNS3_RX_LOW_BYTE_RATE 10000
  1981. #define HNS3_RX_MID_BYTE_RATE 20000
  1982. switch (new_flow_level) {
  1983. case HNS3_FLOW_LOW:
  1984. if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
  1985. new_flow_level = HNS3_FLOW_MID;
  1986. break;
  1987. case HNS3_FLOW_MID:
  1988. if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
  1989. new_flow_level = HNS3_FLOW_HIGH;
  1990. else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
  1991. new_flow_level = HNS3_FLOW_LOW;
  1992. break;
  1993. case HNS3_FLOW_HIGH:
  1994. case HNS3_FLOW_ULTRA:
  1995. default:
  1996. if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
  1997. new_flow_level = HNS3_FLOW_MID;
  1998. break;
  1999. }
  2000. #define HNS3_RX_ULTRA_PACKET_RATE 40
  2001. if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
  2002. &tqp_vector->rx_group == ring_group)
  2003. new_flow_level = HNS3_FLOW_ULTRA;
  2004. switch (new_flow_level) {
  2005. case HNS3_FLOW_LOW:
  2006. new_int_gl = HNS3_INT_GL_50K;
  2007. break;
  2008. case HNS3_FLOW_MID:
  2009. new_int_gl = HNS3_INT_GL_20K;
  2010. break;
  2011. case HNS3_FLOW_HIGH:
  2012. new_int_gl = HNS3_INT_GL_18K;
  2013. break;
  2014. case HNS3_FLOW_ULTRA:
  2015. new_int_gl = HNS3_INT_GL_8K;
  2016. break;
  2017. default:
  2018. break;
  2019. }
  2020. ring_group->total_bytes = 0;
  2021. ring_group->total_packets = 0;
  2022. ring_group->coal.flow_level = new_flow_level;
  2023. if (new_int_gl != ring_group->coal.int_gl) {
  2024. ring_group->coal.int_gl = new_int_gl;
  2025. return true;
  2026. }
  2027. return false;
  2028. }
  2029. static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
  2030. {
  2031. struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
  2032. struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
  2033. bool rx_update, tx_update;
  2034. if (tqp_vector->int_adapt_down > 0) {
  2035. tqp_vector->int_adapt_down--;
  2036. return;
  2037. }
  2038. if (rx_group->coal.gl_adapt_enable) {
  2039. rx_update = hns3_get_new_int_gl(rx_group);
  2040. if (rx_update)
  2041. hns3_set_vector_coalesce_rx_gl(tqp_vector,
  2042. rx_group->coal.int_gl);
  2043. }
  2044. if (tx_group->coal.gl_adapt_enable) {
  2045. tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
  2046. if (tx_update)
  2047. hns3_set_vector_coalesce_tx_gl(tqp_vector,
  2048. tx_group->coal.int_gl);
  2049. }
  2050. tqp_vector->last_jiffies = jiffies;
  2051. tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
  2052. }
  2053. static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
  2054. {
  2055. struct hns3_enet_ring *ring;
  2056. int rx_pkt_total = 0;
  2057. struct hns3_enet_tqp_vector *tqp_vector =
  2058. container_of(napi, struct hns3_enet_tqp_vector, napi);
  2059. bool clean_complete = true;
  2060. int rx_budget;
  2061. /* Since the actual Tx work is minimal, we can give the Tx a larger
  2062. * budget and be more aggressive about cleaning up the Tx descriptors.
  2063. */
  2064. hns3_for_each_ring(ring, tqp_vector->tx_group) {
  2065. if (!hns3_clean_tx_ring(ring, budget))
  2066. clean_complete = false;
  2067. }
  2068. /* make sure rx ring budget not smaller than 1 */
  2069. rx_budget = max(budget / tqp_vector->num_tqps, 1);
  2070. hns3_for_each_ring(ring, tqp_vector->rx_group) {
  2071. int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
  2072. hns3_rx_skb);
  2073. if (rx_cleaned >= rx_budget)
  2074. clean_complete = false;
  2075. rx_pkt_total += rx_cleaned;
  2076. }
  2077. tqp_vector->rx_group.total_packets += rx_pkt_total;
  2078. if (!clean_complete)
  2079. return budget;
  2080. napi_complete(napi);
  2081. hns3_update_new_int_gl(tqp_vector);
  2082. hns3_mask_vector_irq(tqp_vector, 1);
  2083. return rx_pkt_total;
  2084. }
  2085. static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
  2086. struct hnae3_ring_chain_node *head)
  2087. {
  2088. struct pci_dev *pdev = tqp_vector->handle->pdev;
  2089. struct hnae3_ring_chain_node *cur_chain = head;
  2090. struct hnae3_ring_chain_node *chain;
  2091. struct hns3_enet_ring *tx_ring;
  2092. struct hns3_enet_ring *rx_ring;
  2093. tx_ring = tqp_vector->tx_group.ring;
  2094. if (tx_ring) {
  2095. cur_chain->tqp_index = tx_ring->tqp->tqp_index;
  2096. hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
  2097. HNAE3_RING_TYPE_TX);
  2098. hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
  2099. HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
  2100. cur_chain->next = NULL;
  2101. while (tx_ring->next) {
  2102. tx_ring = tx_ring->next;
  2103. chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
  2104. GFP_KERNEL);
  2105. if (!chain)
  2106. goto err_free_chain;
  2107. cur_chain->next = chain;
  2108. chain->tqp_index = tx_ring->tqp->tqp_index;
  2109. hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
  2110. HNAE3_RING_TYPE_TX);
  2111. hnae3_set_field(chain->int_gl_idx,
  2112. HNAE3_RING_GL_IDX_M,
  2113. HNAE3_RING_GL_IDX_S,
  2114. HNAE3_RING_GL_TX);
  2115. cur_chain = chain;
  2116. }
  2117. }
  2118. rx_ring = tqp_vector->rx_group.ring;
  2119. if (!tx_ring && rx_ring) {
  2120. cur_chain->next = NULL;
  2121. cur_chain->tqp_index = rx_ring->tqp->tqp_index;
  2122. hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
  2123. HNAE3_RING_TYPE_RX);
  2124. hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
  2125. HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
  2126. rx_ring = rx_ring->next;
  2127. }
  2128. while (rx_ring) {
  2129. chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
  2130. if (!chain)
  2131. goto err_free_chain;
  2132. cur_chain->next = chain;
  2133. chain->tqp_index = rx_ring->tqp->tqp_index;
  2134. hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
  2135. HNAE3_RING_TYPE_RX);
  2136. hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
  2137. HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
  2138. cur_chain = chain;
  2139. rx_ring = rx_ring->next;
  2140. }
  2141. return 0;
  2142. err_free_chain:
  2143. cur_chain = head->next;
  2144. while (cur_chain) {
  2145. chain = cur_chain->next;
  2146. devm_kfree(&pdev->dev, cur_chain);
  2147. cur_chain = chain;
  2148. }
  2149. head->next = NULL;
  2150. return -ENOMEM;
  2151. }
  2152. static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
  2153. struct hnae3_ring_chain_node *head)
  2154. {
  2155. struct pci_dev *pdev = tqp_vector->handle->pdev;
  2156. struct hnae3_ring_chain_node *chain_tmp, *chain;
  2157. chain = head->next;
  2158. while (chain) {
  2159. chain_tmp = chain->next;
  2160. devm_kfree(&pdev->dev, chain);
  2161. chain = chain_tmp;
  2162. }
  2163. }
  2164. static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
  2165. struct hns3_enet_ring *ring)
  2166. {
  2167. ring->next = group->ring;
  2168. group->ring = ring;
  2169. group->count++;
  2170. }
  2171. static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
  2172. {
  2173. struct hnae3_handle *h = priv->ae_handle;
  2174. struct hns3_enet_tqp_vector *tqp_vector;
  2175. int ret = 0;
  2176. int i;
  2177. for (i = 0; i < priv->vector_num; i++) {
  2178. tqp_vector = &priv->tqp_vector[i];
  2179. hns3_vector_gl_rl_init_hw(tqp_vector, priv);
  2180. tqp_vector->num_tqps = 0;
  2181. }
  2182. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2183. u16 vector_i = i % priv->vector_num;
  2184. u16 tqp_num = h->kinfo.num_tqps;
  2185. tqp_vector = &priv->tqp_vector[vector_i];
  2186. hns3_add_ring_to_group(&tqp_vector->tx_group,
  2187. priv->ring_data[i].ring);
  2188. hns3_add_ring_to_group(&tqp_vector->rx_group,
  2189. priv->ring_data[i + tqp_num].ring);
  2190. priv->ring_data[i].ring->tqp_vector = tqp_vector;
  2191. priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
  2192. tqp_vector->num_tqps++;
  2193. }
  2194. for (i = 0; i < priv->vector_num; i++) {
  2195. struct hnae3_ring_chain_node vector_ring_chain;
  2196. tqp_vector = &priv->tqp_vector[i];
  2197. tqp_vector->rx_group.total_bytes = 0;
  2198. tqp_vector->rx_group.total_packets = 0;
  2199. tqp_vector->tx_group.total_bytes = 0;
  2200. tqp_vector->tx_group.total_packets = 0;
  2201. tqp_vector->handle = h;
  2202. ret = hns3_get_vector_ring_chain(tqp_vector,
  2203. &vector_ring_chain);
  2204. if (ret)
  2205. goto map_ring_fail;
  2206. ret = h->ae_algo->ops->map_ring_to_vector(h,
  2207. tqp_vector->vector_irq, &vector_ring_chain);
  2208. hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
  2209. if (ret)
  2210. goto map_ring_fail;
  2211. netif_napi_add(priv->netdev, &tqp_vector->napi,
  2212. hns3_nic_common_poll, NAPI_POLL_WEIGHT);
  2213. }
  2214. return 0;
  2215. map_ring_fail:
  2216. while (i--)
  2217. netif_napi_del(&priv->tqp_vector[i].napi);
  2218. return ret;
  2219. }
  2220. static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
  2221. {
  2222. #define HNS3_VECTOR_PF_MAX_NUM 64
  2223. struct hnae3_handle *h = priv->ae_handle;
  2224. struct hns3_enet_tqp_vector *tqp_vector;
  2225. struct hnae3_vector_info *vector;
  2226. struct pci_dev *pdev = h->pdev;
  2227. u16 tqp_num = h->kinfo.num_tqps;
  2228. u16 vector_num;
  2229. int ret = 0;
  2230. u16 i;
  2231. /* RSS size, cpu online and vector_num should be the same */
  2232. /* Should consider 2p/4p later */
  2233. vector_num = min_t(u16, num_online_cpus(), tqp_num);
  2234. vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
  2235. vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
  2236. GFP_KERNEL);
  2237. if (!vector)
  2238. return -ENOMEM;
  2239. vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
  2240. priv->vector_num = vector_num;
  2241. priv->tqp_vector = (struct hns3_enet_tqp_vector *)
  2242. devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
  2243. GFP_KERNEL);
  2244. if (!priv->tqp_vector) {
  2245. ret = -ENOMEM;
  2246. goto out;
  2247. }
  2248. for (i = 0; i < priv->vector_num; i++) {
  2249. tqp_vector = &priv->tqp_vector[i];
  2250. tqp_vector->idx = i;
  2251. tqp_vector->mask_addr = vector[i].io_addr;
  2252. tqp_vector->vector_irq = vector[i].vector;
  2253. hns3_vector_gl_rl_init(tqp_vector, priv);
  2254. }
  2255. out:
  2256. devm_kfree(&pdev->dev, vector);
  2257. return ret;
  2258. }
  2259. static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
  2260. {
  2261. group->ring = NULL;
  2262. group->count = 0;
  2263. }
  2264. static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
  2265. {
  2266. struct hnae3_ring_chain_node vector_ring_chain;
  2267. struct hnae3_handle *h = priv->ae_handle;
  2268. struct hns3_enet_tqp_vector *tqp_vector;
  2269. int i, ret;
  2270. for (i = 0; i < priv->vector_num; i++) {
  2271. tqp_vector = &priv->tqp_vector[i];
  2272. ret = hns3_get_vector_ring_chain(tqp_vector,
  2273. &vector_ring_chain);
  2274. if (ret)
  2275. return ret;
  2276. ret = h->ae_algo->ops->unmap_ring_from_vector(h,
  2277. tqp_vector->vector_irq, &vector_ring_chain);
  2278. if (ret)
  2279. return ret;
  2280. hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
  2281. if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
  2282. irq_set_affinity_notifier(tqp_vector->vector_irq,
  2283. NULL);
  2284. irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
  2285. free_irq(tqp_vector->vector_irq, tqp_vector);
  2286. tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
  2287. }
  2288. priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
  2289. hns3_clear_ring_group(&tqp_vector->rx_group);
  2290. hns3_clear_ring_group(&tqp_vector->tx_group);
  2291. netif_napi_del(&priv->tqp_vector[i].napi);
  2292. }
  2293. return 0;
  2294. }
  2295. static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
  2296. {
  2297. struct hnae3_handle *h = priv->ae_handle;
  2298. struct pci_dev *pdev = h->pdev;
  2299. int i, ret;
  2300. for (i = 0; i < priv->vector_num; i++) {
  2301. struct hns3_enet_tqp_vector *tqp_vector;
  2302. tqp_vector = &priv->tqp_vector[i];
  2303. ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
  2304. if (ret)
  2305. return ret;
  2306. }
  2307. devm_kfree(&pdev->dev, priv->tqp_vector);
  2308. return 0;
  2309. }
  2310. static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
  2311. int ring_type)
  2312. {
  2313. struct hns3_nic_ring_data *ring_data = priv->ring_data;
  2314. int queue_num = priv->ae_handle->kinfo.num_tqps;
  2315. struct pci_dev *pdev = priv->ae_handle->pdev;
  2316. struct hns3_enet_ring *ring;
  2317. ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
  2318. if (!ring)
  2319. return -ENOMEM;
  2320. if (ring_type == HNAE3_RING_TYPE_TX) {
  2321. ring_data[q->tqp_index].ring = ring;
  2322. ring_data[q->tqp_index].queue_index = q->tqp_index;
  2323. ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
  2324. } else {
  2325. ring_data[q->tqp_index + queue_num].ring = ring;
  2326. ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
  2327. ring->io_base = q->io_base;
  2328. }
  2329. hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
  2330. ring->tqp = q;
  2331. ring->desc = NULL;
  2332. ring->desc_cb = NULL;
  2333. ring->dev = priv->dev;
  2334. ring->desc_dma_addr = 0;
  2335. ring->buf_size = q->buf_size;
  2336. ring->desc_num = q->desc_num;
  2337. ring->next_to_use = 0;
  2338. ring->next_to_clean = 0;
  2339. return 0;
  2340. }
  2341. static int hns3_queue_to_ring(struct hnae3_queue *tqp,
  2342. struct hns3_nic_priv *priv)
  2343. {
  2344. int ret;
  2345. ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
  2346. if (ret)
  2347. return ret;
  2348. ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
  2349. if (ret) {
  2350. devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
  2351. return ret;
  2352. }
  2353. return 0;
  2354. }
  2355. static int hns3_get_ring_config(struct hns3_nic_priv *priv)
  2356. {
  2357. struct hnae3_handle *h = priv->ae_handle;
  2358. struct pci_dev *pdev = h->pdev;
  2359. int i, ret;
  2360. priv->ring_data = devm_kzalloc(&pdev->dev,
  2361. array3_size(h->kinfo.num_tqps,
  2362. sizeof(*priv->ring_data),
  2363. 2),
  2364. GFP_KERNEL);
  2365. if (!priv->ring_data)
  2366. return -ENOMEM;
  2367. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2368. ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
  2369. if (ret)
  2370. goto err;
  2371. }
  2372. return 0;
  2373. err:
  2374. while (i--) {
  2375. devm_kfree(priv->dev, priv->ring_data[i].ring);
  2376. devm_kfree(priv->dev,
  2377. priv->ring_data[i + h->kinfo.num_tqps].ring);
  2378. }
  2379. devm_kfree(&pdev->dev, priv->ring_data);
  2380. return ret;
  2381. }
  2382. static void hns3_put_ring_config(struct hns3_nic_priv *priv)
  2383. {
  2384. struct hnae3_handle *h = priv->ae_handle;
  2385. int i;
  2386. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2387. devm_kfree(priv->dev, priv->ring_data[i].ring);
  2388. devm_kfree(priv->dev,
  2389. priv->ring_data[i + h->kinfo.num_tqps].ring);
  2390. }
  2391. devm_kfree(priv->dev, priv->ring_data);
  2392. }
  2393. static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
  2394. {
  2395. int ret;
  2396. if (ring->desc_num <= 0 || ring->buf_size <= 0)
  2397. return -EINVAL;
  2398. ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
  2399. GFP_KERNEL);
  2400. if (!ring->desc_cb) {
  2401. ret = -ENOMEM;
  2402. goto out;
  2403. }
  2404. ret = hns3_alloc_desc(ring);
  2405. if (ret)
  2406. goto out_with_desc_cb;
  2407. if (!HNAE3_IS_TX_RING(ring)) {
  2408. ret = hns3_alloc_ring_buffers(ring);
  2409. if (ret)
  2410. goto out_with_desc;
  2411. }
  2412. return 0;
  2413. out_with_desc:
  2414. hns3_free_desc(ring);
  2415. out_with_desc_cb:
  2416. kfree(ring->desc_cb);
  2417. ring->desc_cb = NULL;
  2418. out:
  2419. return ret;
  2420. }
  2421. static void hns3_fini_ring(struct hns3_enet_ring *ring)
  2422. {
  2423. hns3_free_desc(ring);
  2424. kfree(ring->desc_cb);
  2425. ring->desc_cb = NULL;
  2426. ring->next_to_clean = 0;
  2427. ring->next_to_use = 0;
  2428. }
  2429. static int hns3_buf_size2type(u32 buf_size)
  2430. {
  2431. int bd_size_type;
  2432. switch (buf_size) {
  2433. case 512:
  2434. bd_size_type = HNS3_BD_SIZE_512_TYPE;
  2435. break;
  2436. case 1024:
  2437. bd_size_type = HNS3_BD_SIZE_1024_TYPE;
  2438. break;
  2439. case 2048:
  2440. bd_size_type = HNS3_BD_SIZE_2048_TYPE;
  2441. break;
  2442. case 4096:
  2443. bd_size_type = HNS3_BD_SIZE_4096_TYPE;
  2444. break;
  2445. default:
  2446. bd_size_type = HNS3_BD_SIZE_2048_TYPE;
  2447. }
  2448. return bd_size_type;
  2449. }
  2450. static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
  2451. {
  2452. dma_addr_t dma = ring->desc_dma_addr;
  2453. struct hnae3_queue *q = ring->tqp;
  2454. if (!HNAE3_IS_TX_RING(ring)) {
  2455. hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
  2456. (u32)dma);
  2457. hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
  2458. (u32)((dma >> 31) >> 1));
  2459. hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
  2460. hns3_buf_size2type(ring->buf_size));
  2461. hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
  2462. ring->desc_num / 8 - 1);
  2463. } else {
  2464. hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
  2465. (u32)dma);
  2466. hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
  2467. (u32)((dma >> 31) >> 1));
  2468. hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
  2469. ring->desc_num / 8 - 1);
  2470. }
  2471. }
  2472. static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
  2473. {
  2474. struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
  2475. int i;
  2476. for (i = 0; i < HNAE3_MAX_TC; i++) {
  2477. struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
  2478. int j;
  2479. if (!tc_info->enable)
  2480. continue;
  2481. for (j = 0; j < tc_info->tqp_count; j++) {
  2482. struct hnae3_queue *q;
  2483. q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
  2484. hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
  2485. tc_info->tc);
  2486. }
  2487. }
  2488. }
  2489. int hns3_init_all_ring(struct hns3_nic_priv *priv)
  2490. {
  2491. struct hnae3_handle *h = priv->ae_handle;
  2492. int ring_num = h->kinfo.num_tqps * 2;
  2493. int i, j;
  2494. int ret;
  2495. for (i = 0; i < ring_num; i++) {
  2496. ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
  2497. if (ret) {
  2498. dev_err(priv->dev,
  2499. "Alloc ring memory fail! ret=%d\n", ret);
  2500. goto out_when_alloc_ring_memory;
  2501. }
  2502. u64_stats_init(&priv->ring_data[i].ring->syncp);
  2503. }
  2504. return 0;
  2505. out_when_alloc_ring_memory:
  2506. for (j = i - 1; j >= 0; j--)
  2507. hns3_fini_ring(priv->ring_data[j].ring);
  2508. return -ENOMEM;
  2509. }
  2510. int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
  2511. {
  2512. struct hnae3_handle *h = priv->ae_handle;
  2513. int i;
  2514. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2515. if (h->ae_algo->ops->reset_queue)
  2516. h->ae_algo->ops->reset_queue(h, i);
  2517. hns3_fini_ring(priv->ring_data[i].ring);
  2518. hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
  2519. }
  2520. return 0;
  2521. }
  2522. /* Set mac addr if it is configured. or leave it to the AE driver */
  2523. static void hns3_init_mac_addr(struct net_device *netdev, bool init)
  2524. {
  2525. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2526. struct hnae3_handle *h = priv->ae_handle;
  2527. u8 mac_addr_temp[ETH_ALEN];
  2528. if (h->ae_algo->ops->get_mac_addr && init) {
  2529. h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
  2530. ether_addr_copy(netdev->dev_addr, mac_addr_temp);
  2531. }
  2532. /* Check if the MAC address is valid, if not get a random one */
  2533. if (!is_valid_ether_addr(netdev->dev_addr)) {
  2534. eth_hw_addr_random(netdev);
  2535. dev_warn(priv->dev, "using random MAC address %pM\n",
  2536. netdev->dev_addr);
  2537. }
  2538. if (h->ae_algo->ops->set_mac_addr)
  2539. h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
  2540. }
  2541. static void hns3_uninit_mac_addr(struct net_device *netdev)
  2542. {
  2543. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2544. struct hnae3_handle *h = priv->ae_handle;
  2545. if (h->ae_algo->ops->rm_uc_addr)
  2546. h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr);
  2547. }
  2548. static void hns3_nic_set_priv_ops(struct net_device *netdev)
  2549. {
  2550. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2551. if ((netdev->features & NETIF_F_TSO) ||
  2552. (netdev->features & NETIF_F_TSO6)) {
  2553. priv->ops.fill_desc = hns3_fill_desc_tso;
  2554. priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
  2555. } else {
  2556. priv->ops.fill_desc = hns3_fill_desc;
  2557. priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
  2558. }
  2559. }
  2560. static int hns3_client_init(struct hnae3_handle *handle)
  2561. {
  2562. struct pci_dev *pdev = handle->pdev;
  2563. struct hns3_nic_priv *priv;
  2564. struct net_device *netdev;
  2565. int ret;
  2566. netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
  2567. hns3_get_max_available_channels(handle));
  2568. if (!netdev)
  2569. return -ENOMEM;
  2570. priv = netdev_priv(netdev);
  2571. priv->dev = &pdev->dev;
  2572. priv->netdev = netdev;
  2573. priv->ae_handle = handle;
  2574. priv->ae_handle->last_reset_time = jiffies;
  2575. priv->tx_timeout_count = 0;
  2576. handle->kinfo.netdev = netdev;
  2577. handle->priv = (void *)priv;
  2578. hns3_init_mac_addr(netdev, true);
  2579. hns3_set_default_feature(netdev);
  2580. netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
  2581. netdev->priv_flags |= IFF_UNICAST_FLT;
  2582. netdev->netdev_ops = &hns3_nic_netdev_ops;
  2583. SET_NETDEV_DEV(netdev, &pdev->dev);
  2584. hns3_ethtool_set_ops(netdev);
  2585. hns3_nic_set_priv_ops(netdev);
  2586. /* Carrier off reporting is important to ethtool even BEFORE open */
  2587. netif_carrier_off(netdev);
  2588. if (handle->flags & HNAE3_SUPPORT_VF)
  2589. handle->reset_level = HNAE3_VF_RESET;
  2590. else
  2591. handle->reset_level = HNAE3_FUNC_RESET;
  2592. ret = hns3_get_ring_config(priv);
  2593. if (ret) {
  2594. ret = -ENOMEM;
  2595. goto out_get_ring_cfg;
  2596. }
  2597. ret = hns3_nic_alloc_vector_data(priv);
  2598. if (ret) {
  2599. ret = -ENOMEM;
  2600. goto out_alloc_vector_data;
  2601. }
  2602. ret = hns3_nic_init_vector_data(priv);
  2603. if (ret) {
  2604. ret = -ENOMEM;
  2605. goto out_init_vector_data;
  2606. }
  2607. ret = hns3_init_all_ring(priv);
  2608. if (ret) {
  2609. ret = -ENOMEM;
  2610. goto out_init_ring_data;
  2611. }
  2612. ret = register_netdev(netdev);
  2613. if (ret) {
  2614. dev_err(priv->dev, "probe register netdev fail!\n");
  2615. goto out_reg_netdev_fail;
  2616. }
  2617. hns3_dcbnl_setup(handle);
  2618. /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
  2619. netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  2620. return ret;
  2621. out_reg_netdev_fail:
  2622. out_init_ring_data:
  2623. (void)hns3_nic_uninit_vector_data(priv);
  2624. out_init_vector_data:
  2625. hns3_nic_dealloc_vector_data(priv);
  2626. out_alloc_vector_data:
  2627. priv->ring_data = NULL;
  2628. out_get_ring_cfg:
  2629. priv->ae_handle = NULL;
  2630. free_netdev(netdev);
  2631. return ret;
  2632. }
  2633. static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
  2634. {
  2635. struct net_device *netdev = handle->kinfo.netdev;
  2636. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2637. int ret;
  2638. if (netdev->reg_state != NETREG_UNINITIALIZED)
  2639. unregister_netdev(netdev);
  2640. hns3_force_clear_all_rx_ring(handle);
  2641. ret = hns3_nic_uninit_vector_data(priv);
  2642. if (ret)
  2643. netdev_err(netdev, "uninit vector error\n");
  2644. ret = hns3_nic_dealloc_vector_data(priv);
  2645. if (ret)
  2646. netdev_err(netdev, "dealloc vector error\n");
  2647. ret = hns3_uninit_all_ring(priv);
  2648. if (ret)
  2649. netdev_err(netdev, "uninit ring error\n");
  2650. hns3_put_ring_config(priv);
  2651. priv->ring_data = NULL;
  2652. hns3_uninit_mac_addr(netdev);
  2653. free_netdev(netdev);
  2654. }
  2655. static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
  2656. {
  2657. struct net_device *netdev = handle->kinfo.netdev;
  2658. if (!netdev)
  2659. return;
  2660. if (linkup) {
  2661. netif_carrier_on(netdev);
  2662. netif_tx_wake_all_queues(netdev);
  2663. netdev_info(netdev, "link up\n");
  2664. } else {
  2665. netif_carrier_off(netdev);
  2666. netif_tx_stop_all_queues(netdev);
  2667. netdev_info(netdev, "link down\n");
  2668. }
  2669. }
  2670. static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
  2671. {
  2672. struct hnae3_knic_private_info *kinfo = &handle->kinfo;
  2673. struct net_device *ndev = kinfo->netdev;
  2674. bool if_running;
  2675. int ret;
  2676. if (tc > HNAE3_MAX_TC)
  2677. return -EINVAL;
  2678. if (!ndev)
  2679. return -ENODEV;
  2680. if_running = netif_running(ndev);
  2681. if (if_running) {
  2682. (void)hns3_nic_net_stop(ndev);
  2683. msleep(100);
  2684. }
  2685. ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
  2686. kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
  2687. if (ret)
  2688. goto err_out;
  2689. ret = hns3_nic_set_real_num_queue(ndev);
  2690. err_out:
  2691. if (if_running)
  2692. (void)hns3_nic_net_open(ndev);
  2693. return ret;
  2694. }
  2695. static void hns3_recover_hw_addr(struct net_device *ndev)
  2696. {
  2697. struct netdev_hw_addr_list *list;
  2698. struct netdev_hw_addr *ha, *tmp;
  2699. /* go through and sync uc_addr entries to the device */
  2700. list = &ndev->uc;
  2701. list_for_each_entry_safe(ha, tmp, &list->list, list)
  2702. hns3_nic_uc_sync(ndev, ha->addr);
  2703. /* go through and sync mc_addr entries to the device */
  2704. list = &ndev->mc;
  2705. list_for_each_entry_safe(ha, tmp, &list->list, list)
  2706. hns3_nic_mc_sync(ndev, ha->addr);
  2707. }
  2708. static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
  2709. {
  2710. while (ring->next_to_clean != ring->next_to_use) {
  2711. ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
  2712. hns3_free_buffer_detach(ring, ring->next_to_clean);
  2713. ring_ptr_move_fw(ring, next_to_clean);
  2714. }
  2715. }
  2716. static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
  2717. {
  2718. struct hns3_desc_cb res_cbs;
  2719. int ret;
  2720. while (ring->next_to_use != ring->next_to_clean) {
  2721. /* When a buffer is not reused, it's memory has been
  2722. * freed in hns3_handle_rx_bd or will be freed by
  2723. * stack, so we need to replace the buffer here.
  2724. */
  2725. if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
  2726. ret = hns3_reserve_buffer_map(ring, &res_cbs);
  2727. if (ret) {
  2728. u64_stats_update_begin(&ring->syncp);
  2729. ring->stats.sw_err_cnt++;
  2730. u64_stats_update_end(&ring->syncp);
  2731. /* if alloc new buffer fail, exit directly
  2732. * and reclear in up flow.
  2733. */
  2734. netdev_warn(ring->tqp->handle->kinfo.netdev,
  2735. "reserve buffer map failed, ret = %d\n",
  2736. ret);
  2737. return ret;
  2738. }
  2739. hns3_replace_buffer(ring, ring->next_to_use,
  2740. &res_cbs);
  2741. }
  2742. ring_ptr_move_fw(ring, next_to_use);
  2743. }
  2744. return 0;
  2745. }
  2746. static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
  2747. {
  2748. while (ring->next_to_use != ring->next_to_clean) {
  2749. /* When a buffer is not reused, it's memory has been
  2750. * freed in hns3_handle_rx_bd or will be freed by
  2751. * stack, so only need to unmap the buffer here.
  2752. */
  2753. if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
  2754. hns3_unmap_buffer(ring,
  2755. &ring->desc_cb[ring->next_to_use]);
  2756. ring->desc_cb[ring->next_to_use].dma = 0;
  2757. }
  2758. ring_ptr_move_fw(ring, next_to_use);
  2759. }
  2760. }
  2761. static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
  2762. {
  2763. struct net_device *ndev = h->kinfo.netdev;
  2764. struct hns3_nic_priv *priv = netdev_priv(ndev);
  2765. struct hns3_enet_ring *ring;
  2766. u32 i;
  2767. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2768. ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
  2769. hns3_force_clear_rx_ring(ring);
  2770. }
  2771. }
  2772. static void hns3_clear_all_ring(struct hnae3_handle *h)
  2773. {
  2774. struct net_device *ndev = h->kinfo.netdev;
  2775. struct hns3_nic_priv *priv = netdev_priv(ndev);
  2776. u32 i;
  2777. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2778. struct netdev_queue *dev_queue;
  2779. struct hns3_enet_ring *ring;
  2780. ring = priv->ring_data[i].ring;
  2781. hns3_clear_tx_ring(ring);
  2782. dev_queue = netdev_get_tx_queue(ndev,
  2783. priv->ring_data[i].queue_index);
  2784. netdev_tx_reset_queue(dev_queue);
  2785. ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
  2786. /* Continue to clear other rings even if clearing some
  2787. * rings failed.
  2788. */
  2789. hns3_clear_rx_ring(ring);
  2790. }
  2791. }
  2792. int hns3_nic_reset_all_ring(struct hnae3_handle *h)
  2793. {
  2794. struct net_device *ndev = h->kinfo.netdev;
  2795. struct hns3_nic_priv *priv = netdev_priv(ndev);
  2796. struct hns3_enet_ring *rx_ring;
  2797. int i, j;
  2798. int ret;
  2799. for (i = 0; i < h->kinfo.num_tqps; i++) {
  2800. h->ae_algo->ops->reset_queue(h, i);
  2801. hns3_init_ring_hw(priv->ring_data[i].ring);
  2802. /* We need to clear tx ring here because self test will
  2803. * use the ring and will not run down before up
  2804. */
  2805. hns3_clear_tx_ring(priv->ring_data[i].ring);
  2806. priv->ring_data[i].ring->next_to_clean = 0;
  2807. priv->ring_data[i].ring->next_to_use = 0;
  2808. rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
  2809. hns3_init_ring_hw(rx_ring);
  2810. ret = hns3_clear_rx_ring(rx_ring);
  2811. if (ret)
  2812. return ret;
  2813. /* We can not know the hardware head and tail when this
  2814. * function is called in reset flow, so we reuse all desc.
  2815. */
  2816. for (j = 0; j < rx_ring->desc_num; j++)
  2817. hns3_reuse_buffer(rx_ring, j);
  2818. rx_ring->next_to_clean = 0;
  2819. rx_ring->next_to_use = 0;
  2820. }
  2821. hns3_init_tx_ring_tc(priv);
  2822. return 0;
  2823. }
  2824. static void hns3_store_coal(struct hns3_nic_priv *priv)
  2825. {
  2826. /* ethtool only support setting and querying one coal
  2827. * configuation for now, so save the vector 0' coal
  2828. * configuation here in order to restore it.
  2829. */
  2830. memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
  2831. sizeof(struct hns3_enet_coalesce));
  2832. memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
  2833. sizeof(struct hns3_enet_coalesce));
  2834. }
  2835. static void hns3_restore_coal(struct hns3_nic_priv *priv)
  2836. {
  2837. u16 vector_num = priv->vector_num;
  2838. int i;
  2839. for (i = 0; i < vector_num; i++) {
  2840. memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
  2841. sizeof(struct hns3_enet_coalesce));
  2842. memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
  2843. sizeof(struct hns3_enet_coalesce));
  2844. }
  2845. }
  2846. static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
  2847. {
  2848. struct hnae3_knic_private_info *kinfo = &handle->kinfo;
  2849. struct net_device *ndev = kinfo->netdev;
  2850. if (!netif_running(ndev))
  2851. return 0;
  2852. return hns3_nic_net_stop(ndev);
  2853. }
  2854. static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
  2855. {
  2856. struct hnae3_knic_private_info *kinfo = &handle->kinfo;
  2857. int ret = 0;
  2858. if (netif_running(kinfo->netdev)) {
  2859. ret = hns3_nic_net_up(kinfo->netdev);
  2860. if (ret) {
  2861. netdev_err(kinfo->netdev,
  2862. "hns net up fail, ret=%d!\n", ret);
  2863. return ret;
  2864. }
  2865. handle->last_reset_time = jiffies;
  2866. }
  2867. return ret;
  2868. }
  2869. static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
  2870. {
  2871. struct net_device *netdev = handle->kinfo.netdev;
  2872. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2873. int ret;
  2874. hns3_init_mac_addr(netdev, false);
  2875. hns3_nic_set_rx_mode(netdev);
  2876. hns3_recover_hw_addr(netdev);
  2877. /* Hardware table is only clear when pf resets */
  2878. if (!(handle->flags & HNAE3_SUPPORT_VF))
  2879. hns3_restore_vlan(netdev);
  2880. /* Carrier off reporting is important to ethtool even BEFORE open */
  2881. netif_carrier_off(netdev);
  2882. hns3_restore_coal(priv);
  2883. ret = hns3_nic_init_vector_data(priv);
  2884. if (ret)
  2885. return ret;
  2886. ret = hns3_init_all_ring(priv);
  2887. if (ret) {
  2888. hns3_nic_uninit_vector_data(priv);
  2889. priv->ring_data = NULL;
  2890. }
  2891. return ret;
  2892. }
  2893. static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
  2894. {
  2895. struct net_device *netdev = handle->kinfo.netdev;
  2896. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2897. int ret;
  2898. hns3_force_clear_all_rx_ring(handle);
  2899. ret = hns3_nic_uninit_vector_data(priv);
  2900. if (ret) {
  2901. netdev_err(netdev, "uninit vector error\n");
  2902. return ret;
  2903. }
  2904. hns3_store_coal(priv);
  2905. ret = hns3_uninit_all_ring(priv);
  2906. if (ret)
  2907. netdev_err(netdev, "uninit ring error\n");
  2908. hns3_uninit_mac_addr(netdev);
  2909. return ret;
  2910. }
  2911. static int hns3_reset_notify(struct hnae3_handle *handle,
  2912. enum hnae3_reset_notify_type type)
  2913. {
  2914. int ret = 0;
  2915. switch (type) {
  2916. case HNAE3_UP_CLIENT:
  2917. ret = hns3_reset_notify_up_enet(handle);
  2918. break;
  2919. case HNAE3_DOWN_CLIENT:
  2920. ret = hns3_reset_notify_down_enet(handle);
  2921. break;
  2922. case HNAE3_INIT_CLIENT:
  2923. ret = hns3_reset_notify_init_enet(handle);
  2924. break;
  2925. case HNAE3_UNINIT_CLIENT:
  2926. ret = hns3_reset_notify_uninit_enet(handle);
  2927. break;
  2928. default:
  2929. break;
  2930. }
  2931. return ret;
  2932. }
  2933. static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num)
  2934. {
  2935. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2936. struct hnae3_handle *h = hns3_get_handle(netdev);
  2937. int ret;
  2938. ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
  2939. if (ret)
  2940. return ret;
  2941. ret = hns3_get_ring_config(priv);
  2942. if (ret)
  2943. return ret;
  2944. ret = hns3_nic_alloc_vector_data(priv);
  2945. if (ret)
  2946. goto err_alloc_vector;
  2947. hns3_restore_coal(priv);
  2948. ret = hns3_nic_init_vector_data(priv);
  2949. if (ret)
  2950. goto err_uninit_vector;
  2951. ret = hns3_init_all_ring(priv);
  2952. if (ret)
  2953. goto err_put_ring;
  2954. return 0;
  2955. err_put_ring:
  2956. hns3_put_ring_config(priv);
  2957. err_uninit_vector:
  2958. hns3_nic_uninit_vector_data(priv);
  2959. err_alloc_vector:
  2960. hns3_nic_dealloc_vector_data(priv);
  2961. return ret;
  2962. }
  2963. static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
  2964. {
  2965. return (new_tqp_num / num_tc) * num_tc;
  2966. }
  2967. int hns3_set_channels(struct net_device *netdev,
  2968. struct ethtool_channels *ch)
  2969. {
  2970. struct hns3_nic_priv *priv = netdev_priv(netdev);
  2971. struct hnae3_handle *h = hns3_get_handle(netdev);
  2972. struct hnae3_knic_private_info *kinfo = &h->kinfo;
  2973. bool if_running = netif_running(netdev);
  2974. u32 new_tqp_num = ch->combined_count;
  2975. u16 org_tqp_num;
  2976. int ret;
  2977. if (ch->rx_count || ch->tx_count)
  2978. return -EINVAL;
  2979. if (new_tqp_num > hns3_get_max_available_channels(h) ||
  2980. new_tqp_num < kinfo->num_tc) {
  2981. dev_err(&netdev->dev,
  2982. "Change tqps fail, the tqp range is from %d to %d",
  2983. kinfo->num_tc,
  2984. hns3_get_max_available_channels(h));
  2985. return -EINVAL;
  2986. }
  2987. new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
  2988. if (kinfo->num_tqps == new_tqp_num)
  2989. return 0;
  2990. if (if_running)
  2991. hns3_nic_net_stop(netdev);
  2992. ret = hns3_nic_uninit_vector_data(priv);
  2993. if (ret) {
  2994. dev_err(&netdev->dev,
  2995. "Unbind vector with tqp fail, nothing is changed");
  2996. goto open_netdev;
  2997. }
  2998. hns3_store_coal(priv);
  2999. hns3_nic_dealloc_vector_data(priv);
  3000. hns3_uninit_all_ring(priv);
  3001. hns3_put_ring_config(priv);
  3002. org_tqp_num = h->kinfo.num_tqps;
  3003. ret = hns3_modify_tqp_num(netdev, new_tqp_num);
  3004. if (ret) {
  3005. ret = hns3_modify_tqp_num(netdev, org_tqp_num);
  3006. if (ret) {
  3007. /* If revert to old tqp failed, fatal error occurred */
  3008. dev_err(&netdev->dev,
  3009. "Revert to old tqp num fail, ret=%d", ret);
  3010. return ret;
  3011. }
  3012. dev_info(&netdev->dev,
  3013. "Change tqp num fail, Revert to old tqp num");
  3014. }
  3015. open_netdev:
  3016. if (if_running)
  3017. hns3_nic_net_open(netdev);
  3018. return ret;
  3019. }
  3020. static const struct hnae3_client_ops client_ops = {
  3021. .init_instance = hns3_client_init,
  3022. .uninit_instance = hns3_client_uninit,
  3023. .link_status_change = hns3_link_status_change,
  3024. .setup_tc = hns3_client_setup_tc,
  3025. .reset_notify = hns3_reset_notify,
  3026. };
  3027. /* hns3_init_module - Driver registration routine
  3028. * hns3_init_module is the first routine called when the driver is
  3029. * loaded. All it does is register with the PCI subsystem.
  3030. */
  3031. static int __init hns3_init_module(void)
  3032. {
  3033. int ret;
  3034. pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
  3035. pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
  3036. client.type = HNAE3_CLIENT_KNIC;
  3037. snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
  3038. hns3_driver_name);
  3039. client.ops = &client_ops;
  3040. INIT_LIST_HEAD(&client.node);
  3041. ret = hnae3_register_client(&client);
  3042. if (ret)
  3043. return ret;
  3044. ret = pci_register_driver(&hns3_driver);
  3045. if (ret)
  3046. hnae3_unregister_client(&client);
  3047. return ret;
  3048. }
  3049. module_init(hns3_init_module);
  3050. /* hns3_exit_module - Driver exit cleanup routine
  3051. * hns3_exit_module is called just before the driver is removed
  3052. * from memory.
  3053. */
  3054. static void __exit hns3_exit_module(void)
  3055. {
  3056. pci_unregister_driver(&hns3_driver);
  3057. hnae3_unregister_client(&client);
  3058. }
  3059. module_exit(hns3_exit_module);
  3060. MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
  3061. MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
  3062. MODULE_LICENSE("GPL");
  3063. MODULE_ALIAS("pci:hns-nic");
  3064. MODULE_VERSION(HNS3_MOD_VERSION);