gen.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Renesas R-Car Gen1 SRU/SSI support
  4. //
  5. // Copyright (C) 2013 Renesas Solutions Corp.
  6. // Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  7. /*
  8. * #define DEBUG
  9. *
  10. * you can also add below in
  11. * ${LINUX}/drivers/base/regmap/regmap.c
  12. * for regmap debug
  13. *
  14. * #define LOG_DEVICE "xxxx.rcar_sound"
  15. */
  16. #include "rsnd.h"
  17. struct rsnd_gen {
  18. struct rsnd_gen_ops *ops;
  19. /* RSND_BASE_MAX base */
  20. void __iomem *base[RSND_BASE_MAX];
  21. phys_addr_t res[RSND_BASE_MAX];
  22. struct regmap *regmap[RSND_BASE_MAX];
  23. /* RSND_REG_MAX base */
  24. struct regmap_field *regs[RSND_REG_MAX];
  25. const char *reg_name[RSND_REG_MAX];
  26. };
  27. #define rsnd_priv_to_gen(p) ((struct rsnd_gen *)(p)->gen)
  28. #define rsnd_reg_name(gen, id) ((gen)->reg_name[id])
  29. struct rsnd_regmap_field_conf {
  30. int idx;
  31. unsigned int reg_offset;
  32. unsigned int id_offset;
  33. const char *reg_name;
  34. };
  35. #define RSND_REG_SET(id, offset, _id_offset, n) \
  36. { \
  37. .idx = id, \
  38. .reg_offset = offset, \
  39. .id_offset = _id_offset, \
  40. .reg_name = n, \
  41. }
  42. /* single address mapping */
  43. #define RSND_GEN_S_REG(id, offset) \
  44. RSND_REG_SET(RSND_REG_##id, offset, 0, #id)
  45. /* multi address mapping */
  46. #define RSND_GEN_M_REG(id, offset, _id_offset) \
  47. RSND_REG_SET(RSND_REG_##id, offset, _id_offset, #id)
  48. /*
  49. * basic function
  50. */
  51. static int rsnd_is_accessible_reg(struct rsnd_priv *priv,
  52. struct rsnd_gen *gen, enum rsnd_reg reg)
  53. {
  54. if (!gen->regs[reg]) {
  55. struct device *dev = rsnd_priv_to_dev(priv);
  56. dev_err(dev, "unsupported register access %x\n", reg);
  57. return 0;
  58. }
  59. return 1;
  60. }
  61. u32 rsnd_read(struct rsnd_priv *priv,
  62. struct rsnd_mod *mod, enum rsnd_reg reg)
  63. {
  64. struct device *dev = rsnd_priv_to_dev(priv);
  65. struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
  66. u32 val;
  67. if (!rsnd_is_accessible_reg(priv, gen, reg))
  68. return 0;
  69. regmap_fields_read(gen->regs[reg], rsnd_mod_id(mod), &val);
  70. dev_dbg(dev, "r %s[%d] - %-18s (%4d) : %08x\n",
  71. rsnd_mod_name(mod), rsnd_mod_id(mod),
  72. rsnd_reg_name(gen, reg), reg, val);
  73. return val;
  74. }
  75. void rsnd_write(struct rsnd_priv *priv,
  76. struct rsnd_mod *mod,
  77. enum rsnd_reg reg, u32 data)
  78. {
  79. struct device *dev = rsnd_priv_to_dev(priv);
  80. struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
  81. if (!rsnd_is_accessible_reg(priv, gen, reg))
  82. return;
  83. regmap_fields_force_write(gen->regs[reg], rsnd_mod_id(mod), data);
  84. dev_dbg(dev, "w %s[%d] - %-18s (%4d) : %08x\n",
  85. rsnd_mod_name(mod), rsnd_mod_id(mod),
  86. rsnd_reg_name(gen, reg), reg, data);
  87. }
  88. void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod,
  89. enum rsnd_reg reg, u32 mask, u32 data)
  90. {
  91. struct device *dev = rsnd_priv_to_dev(priv);
  92. struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
  93. if (!rsnd_is_accessible_reg(priv, gen, reg))
  94. return;
  95. regmap_fields_force_update_bits(gen->regs[reg],
  96. rsnd_mod_id(mod), mask, data);
  97. dev_dbg(dev, "b %s[%d] - %-18s (%4d) : %08x/%08x\n",
  98. rsnd_mod_name(mod), rsnd_mod_id(mod),
  99. rsnd_reg_name(gen, reg), reg, data, mask);
  100. }
  101. phys_addr_t rsnd_gen_get_phy_addr(struct rsnd_priv *priv, int reg_id)
  102. {
  103. struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
  104. return gen->res[reg_id];
  105. }
  106. #define rsnd_gen_regmap_init(priv, id_size, reg_id, name, conf) \
  107. _rsnd_gen_regmap_init(priv, id_size, reg_id, name, conf, ARRAY_SIZE(conf))
  108. static int _rsnd_gen_regmap_init(struct rsnd_priv *priv,
  109. int id_size,
  110. int reg_id,
  111. const char *name,
  112. const struct rsnd_regmap_field_conf *conf,
  113. int conf_size)
  114. {
  115. struct platform_device *pdev = rsnd_priv_to_pdev(priv);
  116. struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
  117. struct device *dev = rsnd_priv_to_dev(priv);
  118. struct resource *res;
  119. struct regmap_config regc;
  120. struct regmap_field *regs;
  121. struct regmap *regmap;
  122. struct reg_field regf;
  123. void __iomem *base;
  124. int i;
  125. memset(&regc, 0, sizeof(regc));
  126. regc.reg_bits = 32;
  127. regc.val_bits = 32;
  128. regc.reg_stride = 4;
  129. regc.name = name;
  130. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  131. if (!res)
  132. res = platform_get_resource(pdev, IORESOURCE_MEM, reg_id);
  133. if (!res)
  134. return -ENODEV;
  135. base = devm_ioremap_resource(dev, res);
  136. if (IS_ERR(base))
  137. return PTR_ERR(base);
  138. regmap = devm_regmap_init_mmio(dev, base, &regc);
  139. if (IS_ERR(regmap))
  140. return PTR_ERR(regmap);
  141. /* RSND_BASE_MAX base */
  142. gen->base[reg_id] = base;
  143. gen->regmap[reg_id] = regmap;
  144. gen->res[reg_id] = res->start;
  145. for (i = 0; i < conf_size; i++) {
  146. regf.reg = conf[i].reg_offset;
  147. regf.id_offset = conf[i].id_offset;
  148. regf.lsb = 0;
  149. regf.msb = 31;
  150. regf.id_size = id_size;
  151. regs = devm_regmap_field_alloc(dev, regmap, regf);
  152. if (IS_ERR(regs))
  153. return PTR_ERR(regs);
  154. /* RSND_REG_MAX base */
  155. gen->regs[conf[i].idx] = regs;
  156. gen->reg_name[conf[i].idx] = conf[i].reg_name;
  157. }
  158. return 0;
  159. }
  160. /*
  161. * Gen2
  162. */
  163. static int rsnd_gen2_probe(struct rsnd_priv *priv)
  164. {
  165. static const struct rsnd_regmap_field_conf conf_ssiu[] = {
  166. RSND_GEN_S_REG(SSI_MODE0, 0x800),
  167. RSND_GEN_S_REG(SSI_MODE1, 0x804),
  168. RSND_GEN_S_REG(SSI_MODE2, 0x808),
  169. RSND_GEN_S_REG(SSI_CONTROL, 0x810),
  170. RSND_GEN_S_REG(SSI_SYS_STATUS0, 0x840),
  171. RSND_GEN_S_REG(SSI_SYS_STATUS1, 0x844),
  172. RSND_GEN_S_REG(SSI_SYS_STATUS2, 0x848),
  173. RSND_GEN_S_REG(SSI_SYS_STATUS3, 0x84c),
  174. RSND_GEN_S_REG(SSI_SYS_STATUS4, 0x880),
  175. RSND_GEN_S_REG(SSI_SYS_STATUS5, 0x884),
  176. RSND_GEN_S_REG(SSI_SYS_STATUS6, 0x888),
  177. RSND_GEN_S_REG(SSI_SYS_STATUS7, 0x88c),
  178. RSND_GEN_S_REG(HDMI0_SEL, 0x9e0),
  179. RSND_GEN_S_REG(HDMI1_SEL, 0x9e4),
  180. /* FIXME: it needs SSI_MODE2/3 in the future */
  181. RSND_GEN_M_REG(SSI_BUSIF_MODE, 0x0, 0x80),
  182. RSND_GEN_M_REG(SSI_BUSIF_ADINR, 0x4, 0x80),
  183. RSND_GEN_M_REG(SSI_BUSIF_DALIGN,0x8, 0x80),
  184. RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80),
  185. RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80),
  186. RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80),
  187. };
  188. static const struct rsnd_regmap_field_conf conf_scu[] = {
  189. RSND_GEN_M_REG(SRC_I_BUSIF_MODE,0x0, 0x20),
  190. RSND_GEN_M_REG(SRC_O_BUSIF_MODE,0x4, 0x20),
  191. RSND_GEN_M_REG(SRC_BUSIF_DALIGN,0x8, 0x20),
  192. RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20),
  193. RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20),
  194. RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20),
  195. RSND_GEN_M_REG(CMD_BUSIF_MODE, 0x184, 0x20),
  196. RSND_GEN_M_REG(CMD_BUSIF_DALIGN,0x188, 0x20),
  197. RSND_GEN_M_REG(CMD_ROUTE_SLCT, 0x18c, 0x20),
  198. RSND_GEN_M_REG(CMD_CTRL, 0x190, 0x20),
  199. RSND_GEN_S_REG(SCU_SYS_STATUS0, 0x1c8),
  200. RSND_GEN_S_REG(SCU_SYS_INT_EN0, 0x1cc),
  201. RSND_GEN_S_REG(SCU_SYS_STATUS1, 0x1d0),
  202. RSND_GEN_S_REG(SCU_SYS_INT_EN1, 0x1d4),
  203. RSND_GEN_M_REG(SRC_SWRSR, 0x200, 0x40),
  204. RSND_GEN_M_REG(SRC_SRCIR, 0x204, 0x40),
  205. RSND_GEN_M_REG(SRC_ADINR, 0x214, 0x40),
  206. RSND_GEN_M_REG(SRC_IFSCR, 0x21c, 0x40),
  207. RSND_GEN_M_REG(SRC_IFSVR, 0x220, 0x40),
  208. RSND_GEN_M_REG(SRC_SRCCR, 0x224, 0x40),
  209. RSND_GEN_M_REG(SRC_BSDSR, 0x22c, 0x40),
  210. RSND_GEN_M_REG(SRC_BSISR, 0x238, 0x40),
  211. RSND_GEN_M_REG(CTU_SWRSR, 0x500, 0x100),
  212. RSND_GEN_M_REG(CTU_CTUIR, 0x504, 0x100),
  213. RSND_GEN_M_REG(CTU_ADINR, 0x508, 0x100),
  214. RSND_GEN_M_REG(CTU_CPMDR, 0x510, 0x100),
  215. RSND_GEN_M_REG(CTU_SCMDR, 0x514, 0x100),
  216. RSND_GEN_M_REG(CTU_SV00R, 0x518, 0x100),
  217. RSND_GEN_M_REG(CTU_SV01R, 0x51c, 0x100),
  218. RSND_GEN_M_REG(CTU_SV02R, 0x520, 0x100),
  219. RSND_GEN_M_REG(CTU_SV03R, 0x524, 0x100),
  220. RSND_GEN_M_REG(CTU_SV04R, 0x528, 0x100),
  221. RSND_GEN_M_REG(CTU_SV05R, 0x52c, 0x100),
  222. RSND_GEN_M_REG(CTU_SV06R, 0x530, 0x100),
  223. RSND_GEN_M_REG(CTU_SV07R, 0x534, 0x100),
  224. RSND_GEN_M_REG(CTU_SV10R, 0x538, 0x100),
  225. RSND_GEN_M_REG(CTU_SV11R, 0x53c, 0x100),
  226. RSND_GEN_M_REG(CTU_SV12R, 0x540, 0x100),
  227. RSND_GEN_M_REG(CTU_SV13R, 0x544, 0x100),
  228. RSND_GEN_M_REG(CTU_SV14R, 0x548, 0x100),
  229. RSND_GEN_M_REG(CTU_SV15R, 0x54c, 0x100),
  230. RSND_GEN_M_REG(CTU_SV16R, 0x550, 0x100),
  231. RSND_GEN_M_REG(CTU_SV17R, 0x554, 0x100),
  232. RSND_GEN_M_REG(CTU_SV20R, 0x558, 0x100),
  233. RSND_GEN_M_REG(CTU_SV21R, 0x55c, 0x100),
  234. RSND_GEN_M_REG(CTU_SV22R, 0x560, 0x100),
  235. RSND_GEN_M_REG(CTU_SV23R, 0x564, 0x100),
  236. RSND_GEN_M_REG(CTU_SV24R, 0x568, 0x100),
  237. RSND_GEN_M_REG(CTU_SV25R, 0x56c, 0x100),
  238. RSND_GEN_M_REG(CTU_SV26R, 0x570, 0x100),
  239. RSND_GEN_M_REG(CTU_SV27R, 0x574, 0x100),
  240. RSND_GEN_M_REG(CTU_SV30R, 0x578, 0x100),
  241. RSND_GEN_M_REG(CTU_SV31R, 0x57c, 0x100),
  242. RSND_GEN_M_REG(CTU_SV32R, 0x580, 0x100),
  243. RSND_GEN_M_REG(CTU_SV33R, 0x584, 0x100),
  244. RSND_GEN_M_REG(CTU_SV34R, 0x588, 0x100),
  245. RSND_GEN_M_REG(CTU_SV35R, 0x58c, 0x100),
  246. RSND_GEN_M_REG(CTU_SV36R, 0x590, 0x100),
  247. RSND_GEN_M_REG(CTU_SV37R, 0x594, 0x100),
  248. RSND_GEN_M_REG(MIX_SWRSR, 0xd00, 0x40),
  249. RSND_GEN_M_REG(MIX_MIXIR, 0xd04, 0x40),
  250. RSND_GEN_M_REG(MIX_ADINR, 0xd08, 0x40),
  251. RSND_GEN_M_REG(MIX_MIXMR, 0xd10, 0x40),
  252. RSND_GEN_M_REG(MIX_MVPDR, 0xd14, 0x40),
  253. RSND_GEN_M_REG(MIX_MDBAR, 0xd18, 0x40),
  254. RSND_GEN_M_REG(MIX_MDBBR, 0xd1c, 0x40),
  255. RSND_GEN_M_REG(MIX_MDBCR, 0xd20, 0x40),
  256. RSND_GEN_M_REG(MIX_MDBDR, 0xd24, 0x40),
  257. RSND_GEN_M_REG(MIX_MDBER, 0xd28, 0x40),
  258. RSND_GEN_M_REG(DVC_SWRSR, 0xe00, 0x100),
  259. RSND_GEN_M_REG(DVC_DVUIR, 0xe04, 0x100),
  260. RSND_GEN_M_REG(DVC_ADINR, 0xe08, 0x100),
  261. RSND_GEN_M_REG(DVC_DVUCR, 0xe10, 0x100),
  262. RSND_GEN_M_REG(DVC_ZCMCR, 0xe14, 0x100),
  263. RSND_GEN_M_REG(DVC_VRCTR, 0xe18, 0x100),
  264. RSND_GEN_M_REG(DVC_VRPDR, 0xe1c, 0x100),
  265. RSND_GEN_M_REG(DVC_VRDBR, 0xe20, 0x100),
  266. RSND_GEN_M_REG(DVC_VOL0R, 0xe28, 0x100),
  267. RSND_GEN_M_REG(DVC_VOL1R, 0xe2c, 0x100),
  268. RSND_GEN_M_REG(DVC_VOL2R, 0xe30, 0x100),
  269. RSND_GEN_M_REG(DVC_VOL3R, 0xe34, 0x100),
  270. RSND_GEN_M_REG(DVC_VOL4R, 0xe38, 0x100),
  271. RSND_GEN_M_REG(DVC_VOL5R, 0xe3c, 0x100),
  272. RSND_GEN_M_REG(DVC_VOL6R, 0xe40, 0x100),
  273. RSND_GEN_M_REG(DVC_VOL7R, 0xe44, 0x100),
  274. RSND_GEN_M_REG(DVC_DVUER, 0xe48, 0x100),
  275. };
  276. static const struct rsnd_regmap_field_conf conf_adg[] = {
  277. RSND_GEN_S_REG(BRRA, 0x00),
  278. RSND_GEN_S_REG(BRRB, 0x04),
  279. RSND_GEN_S_REG(BRGCKR, 0x08),
  280. RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
  281. RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10),
  282. RSND_GEN_S_REG(AUDIO_CLK_SEL2, 0x14),
  283. RSND_GEN_S_REG(DIV_EN, 0x30),
  284. RSND_GEN_S_REG(SRCIN_TIMSEL0, 0x34),
  285. RSND_GEN_S_REG(SRCIN_TIMSEL1, 0x38),
  286. RSND_GEN_S_REG(SRCIN_TIMSEL2, 0x3c),
  287. RSND_GEN_S_REG(SRCIN_TIMSEL3, 0x40),
  288. RSND_GEN_S_REG(SRCIN_TIMSEL4, 0x44),
  289. RSND_GEN_S_REG(SRCOUT_TIMSEL0, 0x48),
  290. RSND_GEN_S_REG(SRCOUT_TIMSEL1, 0x4c),
  291. RSND_GEN_S_REG(SRCOUT_TIMSEL2, 0x50),
  292. RSND_GEN_S_REG(SRCOUT_TIMSEL3, 0x54),
  293. RSND_GEN_S_REG(SRCOUT_TIMSEL4, 0x58),
  294. RSND_GEN_S_REG(CMDOUT_TIMSEL, 0x5c),
  295. };
  296. static const struct rsnd_regmap_field_conf conf_ssi[] = {
  297. RSND_GEN_M_REG(SSICR, 0x00, 0x40),
  298. RSND_GEN_M_REG(SSISR, 0x04, 0x40),
  299. RSND_GEN_M_REG(SSITDR, 0x08, 0x40),
  300. RSND_GEN_M_REG(SSIRDR, 0x0c, 0x40),
  301. RSND_GEN_M_REG(SSIWSR, 0x20, 0x40),
  302. };
  303. int ret_ssiu;
  304. int ret_scu;
  305. int ret_adg;
  306. int ret_ssi;
  307. ret_ssiu = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SSIU, "ssiu", conf_ssiu);
  308. ret_scu = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SCU, "scu", conf_scu);
  309. ret_adg = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_ADG, "adg", conf_adg);
  310. ret_ssi = rsnd_gen_regmap_init(priv, 10, RSND_GEN2_SSI, "ssi", conf_ssi);
  311. if (ret_ssiu < 0 ||
  312. ret_scu < 0 ||
  313. ret_adg < 0 ||
  314. ret_ssi < 0)
  315. return ret_ssiu | ret_scu | ret_adg | ret_ssi;
  316. return 0;
  317. }
  318. /*
  319. * Gen1
  320. */
  321. static int rsnd_gen1_probe(struct rsnd_priv *priv)
  322. {
  323. static const struct rsnd_regmap_field_conf conf_adg[] = {
  324. RSND_GEN_S_REG(BRRA, 0x00),
  325. RSND_GEN_S_REG(BRRB, 0x04),
  326. RSND_GEN_S_REG(BRGCKR, 0x08),
  327. RSND_GEN_S_REG(AUDIO_CLK_SEL0, 0x0c),
  328. RSND_GEN_S_REG(AUDIO_CLK_SEL1, 0x10),
  329. };
  330. static const struct rsnd_regmap_field_conf conf_ssi[] = {
  331. RSND_GEN_M_REG(SSICR, 0x00, 0x40),
  332. RSND_GEN_M_REG(SSISR, 0x04, 0x40),
  333. RSND_GEN_M_REG(SSITDR, 0x08, 0x40),
  334. RSND_GEN_M_REG(SSIRDR, 0x0c, 0x40),
  335. RSND_GEN_M_REG(SSIWSR, 0x20, 0x40),
  336. };
  337. int ret_adg;
  338. int ret_ssi;
  339. ret_adg = rsnd_gen_regmap_init(priv, 9, RSND_GEN1_ADG, "adg", conf_adg);
  340. ret_ssi = rsnd_gen_regmap_init(priv, 9, RSND_GEN1_SSI, "ssi", conf_ssi);
  341. if (ret_adg < 0 ||
  342. ret_ssi < 0)
  343. return ret_adg | ret_ssi;
  344. return 0;
  345. }
  346. /*
  347. * Gen
  348. */
  349. int rsnd_gen_probe(struct rsnd_priv *priv)
  350. {
  351. struct device *dev = rsnd_priv_to_dev(priv);
  352. struct rsnd_gen *gen;
  353. int ret;
  354. gen = devm_kzalloc(dev, sizeof(*gen), GFP_KERNEL);
  355. if (!gen)
  356. return -ENOMEM;
  357. priv->gen = gen;
  358. ret = -ENODEV;
  359. if (rsnd_is_gen1(priv))
  360. ret = rsnd_gen1_probe(priv);
  361. else if (rsnd_is_gen2(priv) ||
  362. rsnd_is_gen3(priv))
  363. ret = rsnd_gen2_probe(priv);
  364. if (ret < 0)
  365. dev_err(dev, "unknown generation R-Car sound device\n");
  366. return ret;
  367. }